PIC17C44-16/P Microchip Technology, PIC17C44-16/P Datasheet - Page 131

• Manufacturer Part Number: PIC17C44-16/P
• Description: IC MCU OTP 8KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C44-16/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC17
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 33
• Interface Type: SCI/USART
• Number Of Timers: 4
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Ram Size: 454 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Data Rom Size: 454 B
• Height: 4.95 mm
• Length: 53.21 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 14.73 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
1996 Microchip Technology Inc.
After Interrupt
Forced NOP
Decode
PC
GLINTD =
Q1
=
Return from Interrupt
[ label ]
None
TOS
0
PCLATH is unchanged.
Return from Interrupt. Stack is POP’ed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by clearing
the GLINTD bit. GLINTD is the global
interrupt disable bit (CPUSTA<4>).
1
2
RETFIE
GLINTD
register
T0STA
Read
NOP
0000
Q2
TOS
0
GLINTD;
(PC);
RETFIE
0000
Execute
Execute
Q3
0000
NOP
NOP
Q4
0101
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Forced NOP
Decode
WREG
WREG
Q1
=
=
Return Literal to WREG
[ label ]
0
k
PCLATH is unchanged
None
WREG is loaded with the eight bit literal
'k'. The program counter is loaded from
the top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
1
2
TABLE
literal 'k'
Read
NOP
1011
Q2
CALL TABLE ; WREG contains table
:
ADDWF PC
RETLW k0
RETLW k1
:
:
RETLW kn
0x07
value of k7
k
(WREG); TOS
255
PIC17C4X
RETLW k
0110
Execute
Execute
;
;
;
; WREG = offset
; Begin table
;
; End of table
Q3
DS30412C-page 131
offset value
WREG now has
table value
kkkk
(PC);
Write to
WREG
NOP
Q4
kkkk