PIC17C44-16/P Microchip Technology, PIC17C44-16/P Datasheet - Page 39

• Manufacturer Part Number: PIC17C44-16/P
• Description: IC MCU OTP 8KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C44-16/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC17
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 33
• Interface Type: SCI/USART
• Number Of Timers: 4
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Ram Size: 454 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Data Rom Size: 454 B
• Height: 4.95 mm
• Length: 53.21 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 14.73 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6.3
The PIC17C4X devices have a 16 x 16-bit wide hard-
ware stack (Figure 6-1). The stack is not part of either
the program or data memory space, and the stack
pointer is neither readable nor writable. The PC is
“PUSHed” onto the stack when a CALL instruction is
executed or an interrupt is acknowledged. The stack is
“POPed” in the event of a RETURN, RETLW, or a RETFIE
instruction execution. PCLATH is not affected by a
“PUSH” or a “POP” operation.
The stack operates as a circular buffer, with the stack
pointer initialized to '0' after all resets. There is a stack
available bit (STKAV) to allow software to ensure that
the stack has not overflowed. The STKAV bit is set after
a device reset. When the stack pointer equals Fh,
STKAV is cleared. When the stack pointer rolls over
from Fh to 0h, the STKAV bit will be held clear until a
device reset.
After the device is “PUSHed” sixteen times (without a
“POP”), the seventeenth push overwrites the value
from the first push. The eighteenth push overwrites the
second push (and so on).
1996 Microchip Technology Inc.
Note 1: There is not a status bit for stack under-
Note 2: There are no instruction mnemonics
Note 3: After a reset, if a “POP” operation occurs
Stack Operation
flow. The STKAV bit can be used to detect
the underflow which results in the stack
pointer being at the top of stack.
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt vec-
tor.
before a “PUSH” operation, the STKAV bit
will be cleared. This will appear as if the
stack is full (underflow has occurred). If a
“PUSH” operation occurs next (before
another “POP”), the STKAV bit will be
locked clear. Only a device reset will
cause this bit to set.
6.4
Indirect addressing is a mode of addressing data
memory where the data memory address in the
instruction is not fixed. That is, the register that is to be
read or written can be modified by the program. This
can be useful for data tables in the data memory.
Figure 6-10 shows the operation of indirect address-
ing. This shows the moving of the value to the data
memory address specified by the value of the FSR
register.
Example 6-1 shows the use of indirect addressing to
clear RAM in a minimum number of instructions. A
similar concept could be used to move a defined num-
ber of bytes (block) of data to the USART transmit reg-
ister (TXREG). The starting address of the block of
data to be transmitted could easily be modified by the
program.
FIGURE 6-10: INDIRECT ADDRESSING
Instruction
Executed
Instruction
Fetched
Indirect Addressing
Opcode
Opcode
Address
File
PIC17C4X
File = INDFx
DS30412C-page 39
FSR
RAM