UPSD3422EV-40U6 STMicroelectronics, UPSD3422EV-40U6 Datasheet - Page 163

• Manufacturer Part Number: UPSD3422EV-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422EV-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4905

UPSD3422, UPSD3433, UPSD3434, UPSD3454
25.4.3
USB interrupts
There are many USB related events that generate an interrupt. The events that generate an
interrupt are selectively enabled through the use of the USB interrupt enable registers. All
USB interrupts are serviced through a single interrupt vector (see
system on page 62
firmware must check the USB interrupt flag registers to determine the source of the
interrupt, clear that interrupt flag and process the interrupt before returning to the interrupted
code.
The USB interrupt priority can be set to low or high. For the best USB response time and to
maximize data transfer times, the USB interrupt should be set to the highest priority (see the
Section 13: Interrupt system
●
●
●
●
●
Table 104. USB global interrupt enable register (UIE0 0E4h, reset value 00h)
Bit 7
USB Reset Interrupt
The host signals a bus reset by driving both D+ and D– low for at least 10ms. When
the UPSD34xx’s SIE detects a reset on the USB, it generates the RST interrupt
request. A USB reset does not reset the CPU nor the USB SIE, nor does it disable the
USB SIE. The interrupt service routine should disable/enable the USB SIE to reset a
portion of the state machine and initialize the USB SIE registers per the application
requirements.
USB Suspend Interrupt
If the UPSD34xx’s SIE detects 3ms of no activity on the bus, it generates the
SUSPEND interrupt request. It also causes the clock to the SIE to shut down to
conserve power.
USB EOP (End of Packet) Interrupt
Every packet sent on the USB includes a signal, called EOP, to indicate the end of the
packet. When an EOP is detected, the SIE generates an EOP interrupt.
USB Resume Interrupt
When USB activity is detected and the SIE is in the suspend state, a RESUME
interrupt is generated. The USB Resume interrupt service routine should clear the
SUSPENDF bit in the UIF0 register if it is set in order to turn the USB SIE clock on.
USB global interrupt enable register (UIE0)
There are four USB events that are considered to be global in nature, meaning they are
not specific to an endpoint, but apply to the USB bus in general. The four global USB
events include Reset, Suspend, EOP, and Resume.
Each event can be enabled to generate an interrupt using the UIE0 register shown in
Table 104
–
Bit 6
–
for the address of the interrupt vector). When a USB interrupt occurs,
Bit 5
–
for the details on setting the interrupt priority).
Bit 4
–
RSTIE
Bit 3
SUSPENDIE
Bit 2
Section 13: Interrupt
EOPIE
Bit 1
USB interface
RESUMIE
Bit 0
163/300