UPSD3422EV-40U6 STMicroelectronics, UPSD3422EV-40U6 Datasheet - Page 72

MCU 8BIT 8032 64KB FLASH 80TQFP

UPSD3422EV-40U6

Manufacturer Part Number
UPSD3422EV-40U6
Description
MCU 8BIT 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3422EV-40U6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
80KB (80K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4905

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Power saving modes
15
15.1
72/300
Power saving modes
The UPSD34xx is a combination of two die, or modules, each module having its own current
consumption characteristics. This section describes reduced power modes for the MCU
module. See
of the PSD module. Total current consumption for the combined modules is determined in
the DC specifications at the end of this document.
The MCU module has three software-selectable modes of reduced power operation.
Idle mode
Idle mode will halt the 8032 MCU core while leaving the MCU peripherals active (Idle mode
blocks MCU_CLK only). For lowest current consumption in this mode, it is recommended to
disable all unused peripherals, before entering Idle mode (such as the ADC and the Debug
Unit breakpoint comparators). The following functions remain fully active during Idle mode
(except if disabled by SFR settings).
An interrupt generated by any of these peripherals, or a reset generated from the
supervisor, will cause Idle mode to exit and the 8032 MCU will resume normal operation.
The output state on I/O pins of MCU ports 1, 3, and 4 remain unchanged during Idle mode.
To enter Idle mode, the 8032 MCU executes an instruction to set the IDL bit in the SFR
named PCON, shown in
operating mode before Idle mode is activated. Once in Idle mode, the MCU status is entirely
preserved, and there are no changes to: SP, PSW, PC, ACC, SFRs, DATA, IDATA, or XDATA.
The following are factors related to Idle mode exit:
Idle mode
Power-down mode
Reduced frequency mode
External Interrupts INT0 and INT1
Timer 0, Timer 1 and Timer 2
Supervisor reset from: LVD, JTAG Debug, External RESET_IN_, but not the WTD
ADC
I
UART0 and UART1 Interfaces
SPI Interface
Programmable Counter Array
USB Interface
Activation of any enabled interrupt will cause the IDL bit to be cleared by hardware,
terminating Idle mode. The interrupt is serviced, and following the Return from Interrupt
instruction (RETI), the next instruction to be executed will be the one which follows the
instruction that set the IDL bit in the PCON SFR.
After a reset from the supervisor, the IDL bit is cleared, Idle mode is terminated, and
the MCU restarts after three MCU machine cycles.
2
C Interface
Section 28.1.16: Power management on page 197
Table 33 on page
UPSD3422, UPSD3433, UPSD3434, UPSD3454
74. This is the last instruction executed in normal
for reduced power modes

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