UPSD3422EV-40U6 STMicroelectronics, UPSD3422EV-40U6 Datasheet - Page 232

MCU 8BIT 8032 64KB FLASH 80TQFP

UPSD3422EV-40U6

Manufacturer Part Number
UPSD3422EV-40U6
Description
MCU 8BIT 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet

Specifications of UPSD3422EV-40U6

Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
80KB (80K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
For Use With
497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4905

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPSD3422EV-40U6
Manufacturer:
STMicroelectronics
Quantity:
240
Part Number:
UPSD3422EV-40U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
PSD module
232/300
following sections. Some operating modes can be defined using PSDsoft Express, and
some by the 8032 writing to the csiop registers at run-time, and some require both. For
example, PLD I/O, Latched Address Out, and Peripheral I/O modes must be defined in
PSDsoft Express and programmed into the device using JTAG, but an additional step must
happen at run-time to activate Latched Address Out mode and Peripheral I/O mode, but not
needed for PLD I/O. In another example, MCU I/O mode is controlled completely by the
8032 at run-time and only a simple pin name declaration is needed in PSDsoft Express for
documentation.
Table 172 on page 229
actions are required by the 8032 at run-time to achieve the various port functions.
Figure 79. Detail of a single I/O port (typical of ports A, B, C)
Table 176. Port operating modes
MCU I/O
PLD I/O
OMC MCELLAB outputs
OMC MCELLBC outputs
External Chip-Select
outputs
PLD inputs
Port operating mode
From AND-OR array
From PLD input bus
From OMC
allocator
8032
8032 RD
8032
data
8032
WR
data
bits
bit
Latched addr. bit, Port A or B
From OMC output
D bit periph I/O mode, port A
PT Output Enable (.OE)
PSD module reset
summarizes what actions are needed in PSDsoft Express and what
REGIS-
D
CSIOP
TERS
Port A (80-pin
CLR
P
D
B
M
U
X
Q
Q
Q
Q
1
2
3
4
5
6
Direction
Drive
Control
(MCUI/O)
Reset
only)
Data out
registers
One of 6
CSIOP
DIRECTION
DRIVE SELECT
CONTROL
DATA OUT (MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
Yes
Yes
Yes
No
No
Port B
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Yes
Yes
Yes
Yes
No
PSDsoft
Output
Select
1
2
3
4
O
M
U
T
P
U
T
U
X
PERIPH I/O
DATA BIT
Port C
MUX
Yes
OE
Yes
Yes
No
No
WR
(1)
Peripheral I/O
(port A only)
mode sets
RD PIO EN
direction
TO IMC
Port D
Yes
Yes
Yes
No
No
Output Enable
PSELx
Drive type
Output
driver
MCU I/O mode on
PLD I/O mode on
buffer
Input
I/O port
logic
page 233
page 236
Find it
port A, B, C
AI07873b
Typical
pin

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