UPSD3422EV-40U6 STMicroelectronics, UPSD3422EV-40U6 Datasheet - Page 88

• Manufacturer Part Number: UPSD3422EV-40U6
• Description: MCU 8BIT 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3422EV-40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 80KB (80K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5577 - BOARD EVAL USB POWER SWITCH497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4905

MCU bus interface
18.5
88/300
It is not possible to specify in the BUSCON register a different number of MCU_CLK periods
for various address ranges. For example, the user cannot specify 4 MCU_CLK periods for
RD read cycles to one address range on the PSD module, and 5 MCU_CLK periods for RD
read cycles to a different address range on an external device. However, the user can
specify one number of clock periods for PSEN read cycles and a different number of clock
periods for RD or WR cycles (see
Controlling the PFQ and BC
The BUSCON register allows firmware to enable and disable the PFQ and BC at run-time.
Sometimes it may be desired to disable the PFQ and BC to ensure deterministic execution.
The dynamic action of the PFQ and BC may cause varying program execution times
depending on the events that happen prior to a particular section of code of interest. For this
reason, it is not recommended to implement timing loops in firmware, but instead use one of
the many hardware timers in the UPSD34xx. By default, the PFQ and BC are enabled after
a reset condition.
Important note: Disabling the PFQ or BC will seriously reduce MCU performance.
Figure 21. A RD or PSEN bus cycle set to 5 MCU_CLK
1. The PSEN cycle is 16-bit, while the RD cycle is 8-bit only.
2. A PSEN bus cycle in progress may be aborted before completion if the PFQ and Branch Cache (BC)
3. Whenever the same number of MCU_CLK periods is specified in BUSCON for both PSEN and RD cycles,
Table 49.
EPFQ
determines the current code fetch cycle is not needed.
the bus cycle timing is typically identical for each of these types of bus cycles. In this case, the only time
PSEN read cycles are longer than RD read cycles is when the PFQ issues a stall while reloading. PFQ
stalls do not affect RD read cycles. By comparison, in many traditional 8051 architectures, RD bus cycles
are always longer than PSEN bus cycles.
Bit 7
RD/PSEN
MCU Clock
AD0-AD15
BUSCON: bus control register (SFR 9Dh, reset value EBh)
(2,3)
ALE
Bit 6
EBC
Bit 5
1
WRW[1:0]
A0-A15
Figure 21 on page
Bit 4
2
UPSD3422, UPSD3433, UPSD3434, UPSD3454
5-Clock Bus Cycle
Bit 3
3
RDW[1:0]
88).
Bit 2
4
D0-D15 (1)
Bit 1
5
CW[1:0]
AI10436
Bit 0