R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 346

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 14.140 TRDSTR Register in PWM3 Mode
Timer RD Start Register
b7 b6 b5 b4 b3 b2
NOTES:
1.
2.
3.
4.
5.
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD .
When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Nov 26, 2007
b1 b0
Bit Symbol
TSTART0
TSTART1
TRDSTR
(b7-b4)
Symbol
CSEL0
CSEL1
(1)
Page 324 of 580
—
TRD0 count start flag
TRD1 count start flag
TRD0 count operation select bit
TRD1 count operation select bit
[this bit is not used in PWM3 mode]
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Address
Bit Name
0137h
(4)
(5)
0 : Count stops
1 : Count starts
0 : Count stops
1 : Count starts
0 : Count stops at the compare match
1 : Count continues after the compare
0 : Count stops at the compare match
1 : Count continues after the compare
w ith the TRDGRA0 register
match w ith the TRDGRA0 register
w ith the TRDGRA1 register
match w ith the TRDGRA1 register
(2)
(3)
After Reset
11111100b
Function
14. Timers
RW
RW
RW
RW
RW
—