R5F212A8SNFP#U0 Renesas Electronics America, R5F212A8SNFP#U0 Datasheet - Page 450

• Manufacturer Part Number: R5F212A8SNFP#U0
• Description: IC R8C/2A MCU FLASH 64LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/2Ar

Specifications of R5F212A8SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 16.27
IIC bus Control Register 2
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.
Do not w rite during a transfer operation.
This bit is enabled in master mode. When w riting to the BBSY bit, w rite 0 to the SCP bit using the MOV
instruction simultaneously. Execute the same w ay w hen the start condition is regenerating.
This bit is disabled w hen the clock synchronous serial format is used.
Nov 26, 2007
b3 b2 b1
ICCR2 Register
b0
Bit Symbol
SDAOP
Symbol
IICRST
SDAO
ICCR2
SCLO
BBSY
(b0)
(b2)
SCP
Page 428 of 580
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Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
IIC control part reset bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SCL monitor flag
SDAO w rite protect bit
SDA output value control
bit
Start/stop condition
generation disable bit
Bus busy bit
Address
Bit Name
00B9h
(4)
When hang-up occurs due to communication failure
during I
control block of the I
ports or initializing registers.
0 : SCL pin is set to “L”
1 : SCL pin is set to “H”
When rew rite to SDAO bit, w rite 0 simultaneously
When read, the content is 1.
When read
0 : SDA pin output is held “L”
1 : SDA pin output is held “H”
When w ritten
0 : SDA pin output is changed to “L”
1 : SDA pin output is changed to high-impedance
When w riting to the to BBSY bit, w rite 0
simultaneously
When read, the content is 1.
Writing 1 is invalid.
When read
0 : Bus is in released state
1 : Bus is in occupied state
When w ritten
0 : Generates stop condition
1 : Generates start condition
(SDA signal changes from “H” to “L” w hile SCL
(“H” output via external pull-up resistor)
(SDA signal changes from “L” to “H” w hile SCL
signal is in “H” state)
signal is in “H” state)
2
C bus interface operation, w rite 1, to reset the
(1,2)
(3)
(3)
.
2
16. Clock Synchronous Serial Interface
C bus interface w ithout setting
After Reset
01111101b
Function
(1)
.
RW
RW
RW
RW
RW
RW
RO
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