HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 13

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.2
6.3
6.1.60 SHLRn (Shift Logical Right n Bits): Shift Instruction......................................... 242
6.1.61 SLEEP (Sleep): System Control Instruction ........................................................ 244
6.1.62 STC (Store Control Register): System Control Instruction
6.1.63 STS (Store System Register): System Control Instruction
6.1.64 SUB (Subtract Binary): Arithmetic Instruction ................................................... 255
6.1.65 SUBC (Subtract with Carry): Arithmetic Instruction........................................... 256
6.1.66 SUBV (Subtract with V Flag Underflow Check): Arithmetic Instruction ........... 257
6.1.67 SWAP (Swap Register Halves): Data Transfer Instruction ................................. 259
6.1.68 TAS (Test and Set): Logic Operation Instruction ................................................ 261
6.1.69 TRAPA (Trap Always): System Control Instruction ........................................... 262
6.1.70 TST (Test Logical): Logic Operation Instruction ................................................ 264
6.1.71 XOR (Exclusive OR Logical): Logic Operation Instruction................................ 266
6.1.72 XTRCT (Extract): Data Transfer Instruction ....................................................... 268
DSP Data Transfer Instructions......................................................................................... 269
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
DSP Operation Instructions............................................................................................... 283
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10 [if cc] PDMSB (Detect MSB with Condition): DSP Arithmetic Operation
(Interrupt Disabled Instruction)............................................................................ 245
(Interrupt Disabled Instruction)............................................................................ 249
X and Y Data Transfers (MOVX.W and MOVY.W) .......................................... 270
Single Data Transfers (MOVS.W and MOVS.L) ................................................ 272
Sample Description (Name): Classification......................................................... 274
MOVS (Move Single Data between Memory and DSP Register): DSP Data
Transfer Instruction.............................................................................................. 277
MOVX (Move between X Memory and DSP Register): DSP Data Transfer
Instruction ............................................................................................................ 279
MOVY (Move between Y Memory and DSP Register): DSP Data Transfer
Instruction ............................................................................................................ 280
NOPX (No Access Operation for X Memory): DSP Data Transfer Instruction .. 282
NOPY (No Access Operation for Y Memory): DSP Data Transfer Instruction .. 282
PABS (Absolute): DSP Arithmetic Operation Instruction................................... 301
[if cc]PADD (Addition with Condition): DSP Arithmetic Operation Instruction 305
PADD PMULS (Addition & Multiply Signed by Signed): DSP Arithmetic
Operation Instruction ........................................................................................... 309
PADDC (Addition with Carry): DSP Arithmetic Operation Instruction ............. 314
[if cc] PAND (Logical AND): DSP Logical Operation Instruction ..................... 317
[if cc] PCLR (Clear): DSP Arithmetic Operation Instruction .............................. 321
PCMP (Compare Two Data): DSP Arithmetic Operation Instruction ................. 324
[if cc] PCOPY (Copy with Condition): DSP Arithmetic Operation Instruction .. 326
[if cc] PDEC (Decrement by 1): DSP Arithmetic Operation Instruction ............. 331
Instruction ............................................................................................................ 336
Rev. 5.00 Jun 30, 2004 page xi of xiv
REJ09B0171-0500O