HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 385
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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6.3.17
Description: Arithmetically shifts the contents of the Sx or Dz operand and stores the result in the
Dz operand. The amount of the shift is specified by the Sy operand or the immediate value imm
operand. When the shift amount is positive, it shifts left. When the shift amount is negative, it
shifts right. When conditions are specified for DCT and DCF, the instruction is executed when
those conditions are TRUE. When they are FALSE, the instruction is not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. If
conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the conditions were
true and the instruction was executed.
Format
PSHA
Sx,Sy,Dz
DCT PSHA
Sx,Sy,Dz
DCF PSHA
Sx,Sy,Dz
PSHA #imm,Dz if imm
[if cc] PSHA (Shift Arithmetically with Condition): DSP Arithmetic Shift
Instruction
Abstract
if Sy
if Sy 0, Sx
if DC 1 & Sy
Sx
if DC 1 & Sy 0,
Sx
if DC 0, nop
if DC 0 & Sy
Sx
if DC 0 & Sy 0,
Sx
if DC 1, nop
Dz
if imm 0, Dz
Sy Dz
Sy Dz
Sy– Dz
Sy Dz
imm Dz
0, Sx
0,
Sy– Dz
imm Dz
Sy Dz
0,
0,
111110**********
10010001xxyyzzzz
111110**********
10010010xxyyzzzz
111110**********
10010011xxyyzzzz
111110**********
00010iiiiiiizzzz
Code
Rev. 5.00 Jun 30, 2004 page 369 of 512
1
1
1
1
Cycle
Section 6 Instruction Descriptions
DC Bit
Update
Update
—
—
REJ09B0171-0500O
SH-1
—
—
—
—
Instructions
Applicable
SH-2
—
—
—
—
SH-
DSP
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