HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 333

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.5
Description: Does an AND of the upper word of the Sx operand and the upper word of the Sy
operand, stores the result in the upper word of the Dz operand, and clears the bottom word of the
Dz operand with zeros. When Dz is a register that has guard bits, the guard bits are also zeroed.
When conditions are specified for DCT and DCF, the instruction is executed when those
conditions are TRUE. When they are FALSE, the instruction is not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. If
conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the conditions were
true and the instruction was executed.
Note: The bottom word of the destination register and the guard bits are ignored when the DC bit
Operation:
Format
PAND
Sx,Sy,Dz
DCT PAND
Sx,Sy,Dz
DCF PAND
Sx,Sy,Dz
/* PAND Sx,Sy,Dz
{
unsigned char carry_bit, negative_bit, zero_bit, overflow_bit;
/* ALU Sources assignment */
switch (xx) {
is updated.
[if cc] PAND (Logical AND): DSP Logical Operation Instruction
case 0x0: DSP_ALU_SRC1
Abstract
Sx & Sy Dz; clear LSW
of Dz
If DC = 1, SX & SY Dz,
clear LSW of Dz; if 0,
nop
If DC = 0, SX & SY Dz,
clear LSW of Dz; if 1,
nop
break;
/* Sx Operand selection bit (xx) */
*/
Code
111110**********
10010101xxyyzzzz
111110**********
10010110xxyyzzzz
111110**********
10010111xxyyzzzz
= X0;
Rev. 5.00 Jun 30, 2004 page 317 of 512
Cycle
1
1
1
Section 6 Instruction Descriptions
DC
Bit
—
—
SH-1 SH-2
—
—
—
REJ09B0171-0500O
Instructions
Applicable
—
—
—
SH-
DSP