HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 145

• Manufacturer Part Number: HD64F7047F50V
• Description: IC H8 MCU FLASH 256K 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7047r

Specifications of HD64F7047F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Package: 100PQFP
• Family Name: SuperH
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 53
• Interface Type: CAN/SCI
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The PC should point to the location four bytes after the current instruction. Therefore,
means the instruction starts execution from address 0, not address 4.
Examples: Examples are written in assembler mnemonics and describe status before and after
executing the instruction. Characters in italics such as .align are assembler control instructions
(listed below). For more information, see the Cross Assembler User Manual.
Note that the SuperH Family cross assembler version 1.0 does not support the conditional
assembler functions.
Notes: 1. In addressing modes that use the displacements listed below (disp), the assembler
.org
.data.w
.data.l
.sdata
.align 2
.align 4
.arepeat 16
.arepeat 32
.aendr
Definition of bits in SR:
#define M ((*(struct SR0 *)(&SR)).M0)
#define Q ((*(struct SR0 *)(&SR)).Q0)
#define S ((*(struct SR0 *)(&SR)).S0)
#define T ((*(struct SR0 *)(&SR)).T0)
#define RF1 ((*struct SRO *)(&SR)).RF10)
#define RF0 ((*struct SRO *)(&SR)).RF00)
Error display function:
Error( char *er );
statements in this manual show the value prior to scaling ( 1, 2, and 4) according to
the operand size. This is done to clarify the LSI operation. Actual assembler statements
should follow the rules of the assembler in question.
@(disp:4, Rn); Indirect register addressing with displacement
@(disp:8, GBR); Indirect GBR addressing with displacement
Location counter set
Securing integer word data
Securing integer longword data
Securing string data
2-byte boundary alignment
2-byte boundary alignment
16-repeat expansion
32-repeat expansion
End of repeat expansion of specified number
Rev. 5.00 Jun 30, 2004 page 129 of 512
Section 6 Instruction Descriptions
REJ09B0171-0500O
PC = 4;