HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 472
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 7 Pipeline Operation
Double-Length Multiply/Accumulate Instruction (SH-2 CPU, SH-DSP): Includes the
following instruction type:
MAC.L
@Rm+, @Rn+ (SH-2 CPU only)
: Slot
MAC.L
IF
ID
EX
MA
MA mm
mm
mm
mm
EX MA WB
Next instruction
IF
—
ID
Third instruction
IF
ID
EX
MA WB
......
Figure 7.43 Multiply/Accumulate Instruction Pipeline
Operation: The pipeline has nine stages: IF, ID, EX, MA, MA, mm, mm, mm, and mm (figure
7.43). The second MA reads the memory and accesses the multiplier. The mm indicates that the
multiplier is operating. The mm operates for four cycles after the final MA ends, regardless of a
slot. The ID of the instruction after the MAC.L instruction is stalled for one slot. The two MAs of
the MAC.L instruction, when they contend with IF, split the slots as described in Section 7.4,
Contention Between Instruction Fetch (IF) and Memory Access (MA).
When an instruction that does not use the multiplier follows the MAC.L instruction, the MAC.L
instruction may be considered to be five-stage pipeline instructions of IF, ID, EX, MA, and MA.
In such cases, the ID of the next instruction simply stalls one slot and thereafter the pipeline
operates normally. When an instruction that uses the multiplier comes after the MAC.L
instruction, contention occurs with the multiplier, so operation is not as normal. This occurs in the
following cases:
1. When a MAC.L instruction is located immediately after another MAC.L instruction
2. When a MAC.W instruction is located immediately after a MAC.L instruction
3. When a DMULS.L instruction is located immediately after a MAC.L instruction
4. When a MULS.W instruction is located immediately after a MAC.L instruction
5. When an STS (register) instruction is located immediately after a MAC.L instruction
6. When an STS.L (memory) instruction is located immediately after a MAC.L instruction
7. When an LDS (register) instruction is located immediately after a MAC.L instruction
8. When an LDS.L (memory) instruction is located immediately after a MAC.L instruction
Rev. 5.00 Jun 30, 2004 page 456 of 512
REJ09B0171-0500O
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