DF2556FC20DV Renesas Electronics America, DF2556FC20DV Datasheet - Page 234
![IC H8S/2556 MCU FLASH 144QFP](/photos/12/29/122969/df2556fc20dv_sml.jpg)
DF2556FC20DV
Manufacturer Part Number
DF2556FC20DV
Description
IC H8S/2556 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2556FC20DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
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Company:
Part Number:
DF2556FC20DV
Manufacturer:
Renesas Electronics America
Quantity:
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DF2556FC20DV
Manufacturer:
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Quantity:
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Section 8 Data Transfer Controller (DTC)
8.5.5
An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and interrupt controller priority level control.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated after the end of data transfer. The interrupt handling routine will then clear the SWDTE
bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
8.5.6
Figures 8.10 to 8.12 show the DTC operation timing.
Rev. 6.00 Sep. 24, 2009 Page 186 of 928
REJ09B0099-0600
DTC activation
request
DTC
request
Address
φ
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
Interrupts
Operation Timing
Vector read
information read
Transfer
Data transfer
Read Write
information write
Transfer
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