DF2556FC20DV Renesas Electronics America, DF2556FC20DV Datasheet - Page 487
![IC H8S/2556 MCU FLASH 144QFP](/photos/12/29/122969/df2556fc20dv_sml.jpg)
DF2556FC20DV
Manufacturer Part Number
DF2556FC20DV
Description
IC H8S/2556 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2556FC20DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2556FC20DV
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2556FC20DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Clear DR to 0 and set DDR to 1
Write transmit data to TDR and
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
Clear TDRE flag to 0
set MPBT bit in SSR
All data transmitted?
Start transmission
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart
Break output?
Initialization
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1] SCI initialization:
[2] SCI status check and transmit
[3] Serial transmission continuation
[4] Break output at the end of serial
Note: * The case, where the TDRE flag is
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC* is activated by a transmit
data empty interrupt (TXI)
request, and data is written to
TDR.
transmission:
To output a break in serial
transmission, set the port DR to
0, set DDR to 1, then clear the
TE bit in SCR to 0.
Section 13 Serial Communication Interface (SCI)
occurs only when the DISEL bit in DTC is 0
with the transfer counter other than 0.
Therefore, when the DISEL bit is 1, or
both the DISEL bit and the transfer counter are 0,
give the CPU an instruction to clear the TDRE flag.
automatically cleared by DTC,
Rev. 6.00 Sep. 24, 2009 Page 439 of 928
REJ09B0099-0600
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