DF2556FC20DV Renesas Electronics America, DF2556FC20DV Datasheet - Page 685
![IC H8S/2556 MCU FLASH 144QFP](/photos/12/29/122969/df2556fc20dv_sml.jpg)
DF2556FC20DV
Manufacturer Part Number
DF2556FC20DV
Description
IC H8S/2556 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2556FC20DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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DF2556FC20DV
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18.4
18.4.1
The HCAN can be reset by a hardware reset or software reset.
• Hardware Reset
• Software Reset
18.4.2
After a hardware reset, the following initialization processing should be carried out:
1. Clearing of IRR0 bit in the interrupt register (IRR)
2. Bit rate setting
3. Mailbox transmit/receive settings
4. Mailbox (RAM) initialization
5. Message transmission method setting
These initial settings must be made while the HCAN is in bit configuration mode. Configuration
mode is a state in which the GSR3 bit in GSR is set to 1 by a reset. Configuration mode is exited
by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN
automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and
clearing the GSR3 bit because the HCAN needs time to be internally reset, there is a delay
between clearing of the MCR0 bit and GSR3 bit. After the HCAN exits configuration mode, the
power-up sequence begins, and communication with the CAN bus is possible as soon as 11
consecutive recessive bits have been detected.
At power-on reset, or in hardware standby mode, software standby mode, watch mode, or
module stop mode, the HCAN is initialized by automatically setting the MCR reset request bit
(MCR0) in MCR and the reset state bit (GSR3) in GSR. At the same time, all internal
registers, except for message control and message data registers, are initialized by a hardware
reset.
The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In
a software reset, the error counters (TEC and REC) are initialized, however other registers are
not. If the MCR0 bit is set while the CAN controller is performing a communication operation
(transmission or reception), the initialization state is not entered until message transfer has
been completed. The reset status bit (GSR3) in GSR is set on completion of initialization.
Operation
Hardware and Software Resets
Initialization after Hardware Reset
Section 18 Controller Area Network (HCAN) [H8S/2556 Group]
Rev. 6.00 Sep. 24, 2009 Page 637 of 928
REJ09B0099-0600
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