DF2556FC20DV Renesas Electronics America, DF2556FC20DV Datasheet - Page 701
![IC H8S/2556 MCU FLASH 144QFP](/photos/12/29/122969/df2556fc20dv_sml.jpg)
DF2556FC20DV
Manufacturer Part Number
DF2556FC20DV
Description
IC H8S/2556 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2556FC20DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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• Clearing by software
• Clearing by CAN bus operation
Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus
communication is re-enabled.
Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN bus operation: The cancellation method is selected by the MCR7 bit setting in
MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs an
operation and this change is detected. In this case, the first message is not stored in a mailbox;
messages will be received normally from the second message onward. When a change is detected
on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the
interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is
set to the interrupt enable value at this time, an interrupt can be sent to the CPU.
18.4.6
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 18.14 shows a flowchart of the HCAN halt mode.
HCAN Halt Mode
CAN bus communication possible
Figure 18.14 HCAN Halt Mode Flowchart
MBCR setting
MCR1 = 1
MCR1 = 0
Bus idle?
Yes
Section 18 Controller Area Network (HCAN) [H8S/2556 Group]
No
Rev. 6.00 Sep. 24, 2009 Page 653 of 928
: Settings by user
: Processing by hardware
REJ09B0099-0600
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