PIC16C770-I/P Microchip Technology, PIC16C770-I/P Datasheet - Page 96

• Manufacturer Part Number: PIC16C770-I/P
• Description: IC MCU CMOS A/D 2K 20MHZ 20-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C770-I/P

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 16
• Ram Memory Size: 256Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• No. Of: RoHS Compliant
• Core: PIC
• Processor Series: PIC16C
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Data Ram Size: 256 B
• Data Rom Size: 256 B
• On-chip Adc: 6 bit
• Number Of Programmable I/os: 16
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Mounting Style: Through Hole
• Height: 3.3 mm
• Interface Type: I2C, SPI, SSP
• Length: 26.16 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 6.35 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC16C770I/P

PIC16C717/770/771
9.2.17
Multi-master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, bus arbitration is initiated when one mas-
ter outputs a ’1’ on SDA (by letting SDA float high) and
another master asserts a ’0’. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master that
expected a ‘1’ will set the Bus Collision Interrupt Flag,
BCLIF, and reset the I
(Figure 9-23).
A bus collision during transmit results in the following
events:
• The transmission is halted.
• The BF flag is cleared
• The SDA and SCL lines are de-asserted
• The restriction on writing to the SSPBUF during
When the user services the bus collision interrupt ser-
vice routine, and if the I
resume communication by asserting a START condi-
tion.
FIGURE 9-23:
DS41120B-page 94
transmission is lifted.
SDA
SCL
BCLIF
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
2
2
C bus is free, the user can
C port to its IDLE state.
Data changes
while SCL = 0
Advance Information
SDA released
by master
SDA line pulled low
by another source
A bus collision during a START, Repeated START,
STOP or Acknowledge condition results in the following
events:
• The condition is aborted.
• The SDA and SCL lines are de-asserted.
• The respective control bits in the SSPCON2 regis-
When the user services the bus collision interrupt ser-
vice routine, and if the I
resume communication by asserting a START condi-
tion.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
ter are cleared.
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
2
C bus is free, the user can
2002 Microchip Technology Inc.
2
C