ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 122

• Manufacturer Part Number: ATA6616-P3PW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3PW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Atmel ATA6616/ATA6617
• When writing to one of the registers TCNT0, OCR0A, or TCCR0A, the value is transferred
• When entering Power-save mode after having written to TCNT0, OCR0A, or TCCR0A, the
• If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must
• When the asynchronous operation is selected, the oscillator for Timer/Counter0 is always
• Description of wake up from Power-save mode when the timer is clocked asynchronously:
• Reading of the TCNT0 Register shortly after wake-up from Power-save may give an
to a temporary register, and latched after two positive edges on TOSC1. The user should
not write a new value before the contents of the temporary register have been transferred
to its destination. Each of the three mentioned registers have their individual temporary
register, which means that e.g. writing to TCNT0 does not disturb an OCR0A write in
progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented.
user must wait until the written register has been updated if Timer/Counter0 is used to
wake up the device. Otherwise, the MCU will enter sleep mode before the changes are
effective. This is particularly important if the Output Compare0 interrupt is used to wake up
the device, since the Output Compare function is disabled during writing to OCR0A or
TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the
OCR0UB bit returns to zero, the device will never receive a compare match interrupt, and
the MCU will not wake up.
be taken if the user wants to re-enter one of these modes: The interrupt logic needs one
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less
than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the
user is in doubt whether the time before re-entering Power-save mode is sufficient, the
following algorithm can be used to ensure that one TOSC1 cycle has elapsed:
a) Write a value to TCCR0A, TCNT0, or OCR0A.
b) Wait until the corresponding Update Busy flag in ASSR returns to zero.
c) Enter Power-save or ADC Noise Reduction mode.
running, except in Power-down mode. After a Power-up Reset or wake-up from
Power-down mode, the user should be aware of the fact that this oscillator might take as
long as one second to stabilize. The user is advised to wait for at least one second before
using Timer/Counter0 after power-up or wake-up from Power-down mode. The contents of
all Timer/Counter0 Registers must be considered lost after a wake-up from Power-down
mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use
or a clock signal is applied to the XTAL1 pin.
When the interrupt condition is met, the wake up process is started on the following cycle of
the timer clock, that is, the timer is always advanced by at least one before the processor
can read the counter value. After wake-up, the MCU is halted for four cycles, it executes
the interrupt routine, and resumes execution from the instruction following SLEEP.
incorrect result. Since TCNT0 is clocked on the asynchronous clock, reading TCNT0 must
be done through a register synchronized to the internal I/O clock domain (CPU main clock).
Synchronization takes place for every rising XTAL1 edge. When waking up from
Power-save mode, and the I/O clock (clk
previous value (before entering sleep) until the next rising XTAL1 edge. The phase of the
XTAL1 clock after waking up from Power-save mode is essentially unpredictable, as it
depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as
follows:
I/O
) again becomes active, TCNT0 will read as the
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