ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 93

• Manufacturer Part Number: ATA6616-P3PW
• Description: TXRX MULTICHIP MOD LIN SIP 38QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6616-P3PW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 38-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.10.2.4
4.10.2.5
9132D–AUTO–12/10
Switching Between Input and Output
Reading the Pin Value
W h e n s w i t c h i n g b e t w e e n t r i - s t a t e ( { D D x n , P O R T x n } = 0 , 0 ) a n d o u t p u t h i g h
( { D D x n , P O R T x n } = 1 , 1 ) , a n i n t e r m e d i a t e s t a t e w i t h e i t h e r p u l l - u p e n a b l e d
{DDxn, PORTxn} = 0, 1) or output low ({DDxn, PORTxn} = 1, 0) must occur. Normally, the
pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the
MCUCR Register or the PUDx bit in PORTCR Register can be set to disable all pull-ups in the
port.
Switching between input with pull-up and output low generates the same problem. The user
m u s t u s e e it h e r t h e tr i - s t a t e ( { D D x n , P O R T x n } = 0 , 0 ) o r th e o u t p u t h i g h s t a t e
({DDxn, PORTxn} = 1, 1) as an intermediate step.
Table 4-22
Table 4-22.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
constitute a synchronizer. This is needed to avoid metastability if the physical pin changes
value near the edge of the internal clock, but it also introduces a delay.
timing diagram of the synchronization when reading an externally applied pin value. The max-
imum and minimum propagation delays are denoted t
Figure 4-27. Synchronization when Reading an Externally Applied Pin Value
Note:
DDxn
0
0
0
1
1
1. Or port-wise PUDx bit in PORTCR register.
PORTxn
INSTRUCTIONS
summarizes the control signals for the pin value.
SYSTEM CLK
SYNC LATCH
0
1
1
0
1
Port Pin Configurations
PINxn
(in MCUCR)
r17
PUD
X
X
X
0
1
Figure
(1)
XXX
Output
Output
Input
Input
Input
I/O
4-25, the PINxn Register bit and the preceding latch
Atmel ATA6616/ATA6617
t
pd, max
Pull-up Comment
0x00
Yes
No
No
No
No
XXX
t
pd,max
pd, min
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
and t
in r17, PINx
pd,min
respectively.
Figure 4-27
0xFF
shows a
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