ATA6616-P3PW Atmel, ATA6616-P3PW Datasheet - Page 223

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ATA6616-P3PW

Manufacturer Part Number
ATA6616-P3PW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6616-P3PW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4.18.7.2
4.18.7.3
9132D–AUTO–12/10
Analog Noise Canceling Techniques
ADC Accuracy Definitions
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
An n-bit single-ended ADC converts a voltage linearly between GND and V
(LSBs). The lowest code is read as 0, and the highest code is read as 2
Several parameters describe the deviation from the ideal behavior:
Figure 4-90. Offset Error
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
(at 0.5 LSB). Ideal value: 0 LSB.
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum).
Ideal value: 0 LSB
a. Keep analog signal paths as short as possible. Make sure analog tracks run over
b. Use the ADC noise canceler function to reduce induced noise from the CPU.
c. If any port pins are used as digital outputs, it is essential that these do not switch
the analog ground plane, and keep them well away from high-speed switching
digital tracks.
while a conversion is in progress.
Output Code
Offset
Error
Atmel ATA6616/ATA6617
V
REF
Input Voltage
n
Ideal ADC
Actual ADC
-1.
REF
in 2
n
steps
223

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