ATTINY261-15MZ Atmel, ATTINY261-15MZ Datasheet - Page 128

• Manufacturer Part Number: ATTINY261-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17. USI – Universal Serial Interface
17.1
17.2
128
Features
Overview
ATtiny261/ATtiny461/ATtiny861
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The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown on Figure 17-1. For the actual placement of I/O
pins, refer to
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the
Figure 17-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register is directly accessible via the data bus and contains the incoming
and outgoing data. The register has no buffering so the data must be read as quickly as possible
to ensure that no data is lost. The USI Data Register is a serial shift register and the most signif-
icant bit that is the output of the serial shift register is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the USI Data
Register Output and output pin, which delays the change of data output to the opposite clock
edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“Register Descriptions” on page
“Pinout ATtiny261/461/861” on page
USIDR
USICR
USIDB
USISR
2
4-bit Counter
135.
3
2
1
0
3
2
1
0
D Q
LE
[1]
TIM0 COMP
2. CPU accessible I/O Registers, including I/O
0
1
Two-wire Clock
Control Unit
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
(Output only)
(Input/Open Drain)
(Input/Open Drain)
7753F–AVR–01/11