ATTINY261-15MZ Atmel, ATTINY261-15MZ Datasheet - Page 71

• Manufacturer Part Number: ATTINY261-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.1
13.1.1
7753F–AVR–01/11
Register Description
TCCR0B – Timer/Counter0 Control Register B
However, due to variation of the system clock frequency and duty cycle caused by Oscillator
source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum fre-
quency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0
Note:
• Bit 4 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by
hardware, and the Timer/Counter start counting.
• Bit 3 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0
The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer0.
Bit
0x33 (0x53)
Read/Write
Initial Value
1. The synchronization logic on the input pins (
PSR0
clk
T0
I/O
R
7
0
-
Synchronization
R
6
0
-
R
5
0
-
Clear
ATtiny261/ATtiny461/ATtiny861
TSM
R/W
4
0
clk_I/O
T0)
PSR0
R/W
/2.5.
3
0
is shown in
CS02
R/W
2
0
Figure
clk
T0
CS01
R/W
13-1.
1
0
CS01
R/W
0
0
TCCR0B
71