ATTINY261-15MZ Atmel, ATTINY261-15MZ Datasheet - Page 77

• Manufacturer Part Number: ATTINY261-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6
7753F–AVR–01/11
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul-
tiple events, can be applied via the ICP0 pin or alternatively, via the analog-comparator unit. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-
nal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in
the block diagram that are not directly a part of the Input Capture unit are gray shaded.
Figure 14-3. Input Capture Unit Block Diagram
The Output Compare Register OCR0A is a dual-purpose register that is also used as an 8-bit
Input Capture Register ICR0. In 16-bit Input Capture mode the Output Compare Register
OCR0B serves as the high byte of the Input Capture Register ICR0. In 8-bit Input Capture mode
the Output Compare Register OCR0B is free to be used as a normal Output Compare Register,
but in 16-bit Input Capture mode the Output Compare Unit cannot be used as there are no free
Output Compare Register(s). Even though the Input Capture register is called ICR0 in this sec-
tion, it is referring to the Output Compare Register(s).
When a change of the logic level (an event) occurs on the Input Capture pin (ICP0), alternatively
on the Analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the value of the counter
(TCNT0) is written to the Input Capture Register (ICR0). The Input Capture Flag (ICF0) is set at
the same system clock as the TCNT0 value is copied into Input Capture Register. If enabled
(TICIE0=1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is auto-
matically cleared when the interrupt is executed. Alternatively the ICF0 flag can be cleared by
software by writing a logical one to its I/O bit location.
ICP0
WRITE
OCR0B (8-bit)
TEMP (8-bit)
Comparator
Analog
ICR0 (16-bit Register)
ACO*
OCR0A (8-bit)
ATtiny261/ATtiny461/ATtiny861
ACIC0*
DATA BUS
Canceler
ICNC0
Noise
(8-bit)
TCNT0H (8-bit)
TCNT0 (16-bit Counter)
Detector
ICES0
Edge
Figure
TCNT0L (8-bit)
14-3. The elements of
ICF0 (Int.Req.)
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