ATTINY261-15MZ Atmel, ATTINY261-15MZ Datasheet - Page 96

• Manufacturer Part Number: ATTINY261-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3
16.3.1
96
Counter Unit
ATtiny261/ATtiny461/ATtiny861
Counter Initialization for Asynchronous Mode
The main part of the Timer/Counter1 is the programmable bi-directional counter unit.
shows a block diagram of the counter and its surroundings.
Figure 16-3. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
asynchronous PLL clock using the Clock Select bits (CS13:0) and the PCK Enable bit (PCKE).
When no clock source is selected (CS13:0 = 0) the timer is stopped. However, the TCNT1 value
can be accessed by the CPU, regardless of whether clk
rides (has priority over) all counter clear or count operations.
The counting sequence of the Timer/Counter1 is determined by the setting of the WGM10 and
PWM1x bits located in the Timer/Counter1 Control Registers (TCCR1A, TCCR1C and
TCCR1D). For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
the mode of operation selected by the PWM1x and WGM10 bits. The Overflow Flag can be used
for generating a CPU interrupt.
To change Timer/Counter1 to the asynchronous mode follow the procedure below:
1. Enable PLL.
2. Wait 100 µs for PLL to stabilize.
3. Poll the PLOCK bit until it is set.
4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNT1
T1
). The timer clock is generated from an synchronous system clock or an
TCNT1 increment or decrement enable.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
102. The Timer/Counter Overflow Flag (TOV1) is set according to
direction
count
clk
clear
T1
bottom
Control Logic
T1
top
is present or not. A CPU write over-
TOV1
T1
PCKE
PCK
Timer/Counter1 Count Enable
( From Prescaler )
CK
in the following.
7753F–AVR–01/11
Figure 16-3