ATTINY261-15MZ Atmel, ATTINY261-15MZ Datasheet - Page 90

• Manufacturer Part Number: ATTINY261-15MZ
• Description: MCU AVR 2K FLASH 15MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY261-15MZ

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 2KB (2K x 8)
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.1
15.1.1
15.1.2
90
Register Description
ATtiny261/ATtiny461/ATtiny861
PLLCSR – PLL Control and Status Register
TCCR1B – Timer/Counter1 Control Register B
• Bit 7- LSM: Low Speed Mode
The Low Speed mode is set, if the LSM bit is written to one. Then the fast peripheral clock is
scaled down to 32 MHz. The Low Speed Mode must be set, if the supply voltage is below 2.7
volts, because the Timer/Counter1 is not running fast enough on low voltage levels. It is recom-
mended that the Timer/Counter1 is stopped whenever the LSM bit is changed.
Note, that LSM can not be set if PLL
• Bit 6:3- Res: Reserved Bits
These bits are reserved bits in the ATtiny261/461/861 and always read as zero.
• Bit 2- PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock
mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as a
Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and
system clock CK is used as Timer/Counter1 clock source. It is safe to set this bit only when the
PLL is locked i.e the PLOCK bit is 1. Note that the PCKE bit can be set only, if the PLL has been
enabled earlier. The PLL is enabled when the CKSEL fuse has been programmed to 0x0001
(the PLL clock mode is selected) or the PLLE bit has been set to one.
• Bit 1- PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0- PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be
ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots,
before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is
recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.
• Bit 7 - Res: Reserved Bit
• Bit 6 - PSR1: Prescaler Reset Timer/Counter1
Bit
0x29 (0x49)
Read/Write
Initial value
Bit
0x2F (0x4F)
Read/Write
Initial value
7
LSM
R/W
0
7
-
R/W
0
6
-
R
0
6
PSR1
R/W
0
5
DTPS11
R/W
0
5
-
R
0
CLK
is used as a system clock.
4
-
R
0
4
DTPS10
R/W
0
3
CS13
R/W
0
3
-
R
0
2
CS12
R/W
0
2
PCKE
R/W
0
1
PLLE
R/W
0/1
1
CS11
R/W
0
0
CS10
R/W
0
0
PLOCK
R
0
7753F–AVR–01/11
TCCR1B
PLLCSR