PIC16F870T-I/SS Microchip Technology, PIC16F870T-I/SS Datasheet - Page 103

• Manufacturer Part Number: PIC16F870T-I/SS
• Description: IC MCU FLASH 2KX14 EE 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F870T-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• For Use With: I3-DB16F871 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 11-11:
11.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is pro-
grammed to a '0', the In-Circuit Debugger functionality
is enabled. This function allows simple debugging func-
tions when used with MPLAB
controller has this feature enabled, some of the
resources are not available for general use. Table 11-8
shows
background debugger.
TABLE 11-8:
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.
 2003 Microchip Technology Inc.
I/O pins
Stack
Program Memory
Data Memory
OSC1
CLKO
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
Note 1: XT, HS or LP Oscillator mode assumed.
(4)
2: T
3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4: CLKO is not available in these Osc modes, but shown here for timing reference.
which
PC
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
= 1024 T
Inst(PC - 1)
features
DEBUGGER RESOURCES
PC
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
RB6, RB7
1 level
Address 0000h must be NOP
Last 100h words
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
(drawing not to scale). This delay will not be there for RC Osc mode.
are
®
Inst(PC + 1)
SLEEP
PC+1
ICD. When the micro-
consumed
PP
Processor in
, V
SLEEP
DD
by
, GND,
PC+2
the
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
11.15 Program Verification/Code
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
PC+2
Protection
Interrupt Latency
Dummy cycle
PC + 2
PIC16F870/871
(2)
Inst(0004h)
Dummy cycle
0004h
DS30569B-page 101
Inst(0005h)
Inst(0004h)
0005h