PIC16F870T-I/SS Microchip Technology, PIC16F870T-I/SS Datasheet - Page 167

• Manufacturer Part Number: PIC16F870T-I/SS
• Description: IC MCU FLASH 2KX14 EE 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F870T-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• For Use With: I3-DB16F871 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STATUS Register ......................................................... 13, 15
Synchronous Master Reception
Synchronous Master Transmission
Synchronous Slave Reception
Synchronous Slave Transmission
T
T1CKPS0 Bit ....................................................................... 49
T1CKPS1 Bit ....................................................................... 49
T1CON Register ................................................................. 13
T1OSCEN Bit ...................................................................... 49
T1SYNC Bit......................................................................... 49
T2CKPS0 Bit ....................................................................... 53
T2CKPS1 Bit ....................................................................... 53
T2CON Register ................................................................. 13
T
Time-out Sequence............................................................. 92
Timer0 ................................................................................. 45
Timer1 ................................................................................. 49
Timer2 ................................................................................. 53
Timing Diagrams
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AD
...................................................................................... 83
PD Bit.......................................................................... 91
TO Bit.......................................................................... 91
Associated Registers .................................................. 75
Associated Registers .................................................. 73
Associated Registers .................................................. 77
Associated Registers .................................................. 76
Associated Registers .................................................. 47
Clock Source Edge Select (T0SE Bit)......................... 17
Clock Source Select (T0CS Bit).................................. 17
External Clock............................................................. 46
Interrupt....................................................................... 45
Overflow Enable (T0IE Bit) ......................................... 18
Overflow Flag (T0IF Bit).............................................. 97
Overflow Interrupt ....................................................... 97
Prescaler..................................................................... 46
T0CKI.......................................................................... 46
Associated Registers .................................................. 52
Asynchronous Counter Mode
Counter Operation ...................................................... 50
Incrementing Edge (figure) ......................................... 50
Operation in Asynchronous Counter Mode................. 51
Operation in Synchronized Counter Mode.................. 50
Operation in Timer Mode ............................................ 50
Oscillator ..................................................................... 51
Prescaler..................................................................... 52
Resetting of Timer1 Register Pair
Resetting Timer1 Using a CCP Trigger Output........... 51
TMR1H........................................................................ 51
TMR1L ........................................................................ 51
Associated Registers .................................................. 54
Output ......................................................................... 54
Postscaler ................................................................... 53
Prescaler..................................................................... 53
Prescaler and Postscaler ............................................ 54
A/D Conversion......................................................... 135
Asynchronous Master Transmission........................... 67
Asynchronous Master Transmission
Asynchronous Reception with
Reading and Writing to ....................................... 51
Capacitor Selection............................................. 51
(TMR1H, TMR1L) ............................................... 52
(Back to Back) .................................................... 67
Address Byte First .............................................. 71
Timing Parameter Symbology .......................................... 125
TMR0 Register.............................................................. 13, 15
TMR1CS Bit........................................................................ 49
TMR1H Register ................................................................. 13
TMR1L Register.................................................................. 13
TMR1ON Bit ....................................................................... 49
TMR2 Register.................................................................... 13
TMR2ON Bit ....................................................................... 53
TOUTPS0 Bit ...................................................................... 53
TOUTPS1 Bit ...................................................................... 53
TOUTPS2 Bit ...................................................................... 53
TOUTPS3 Bit ...................................................................... 53
TRISA ................................................................................. 15
TRISA Register................................................................... 14
TRISB ................................................................................. 15
TRISB Register............................................................. 14, 15
TRISC ................................................................................. 15
TRISC Register................................................................... 14
TRISD ................................................................................. 15
TRISD Register................................................................... 14
TRISE ................................................................................. 15
TRISE Register................................................................... 14
TXREG Register ................................................................. 13
TXSTA ................................................................................ 15
TXSTA Register.................................................................. 14
Asynchronous Reception with
Brown-out Reset....................................................... 129
Capture/Compare/PWM (CCP1) .............................. 131
CLKO and I/O ........................................................... 128
External Clock .......................................................... 126
Parallel Slave Port (PSP) Read.................................. 43
Parallel Slave Port (PSP) Write .................................. 43
RESET, Watchdog Timer, Oscillator
Slow Rise Time (MCLR Tied to V
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock ........................... 130
USART Asynchronous Reception .............................. 68
USART Synchronous Receive (Master/Slave) ......... 133
USART Synchronous Reception
USART Synchronous Transmission ........................... 73
USART Synchronous Transmission
Wake-up from SLEEP via Interrupt .......................... 101
IBF Bit......................................................................... 40
IBOV Bit...................................................................... 40
OBF Bit ....................................................................... 40
PSPMODE Bit .......................................... 38, 39, 40, 42
BRGH Bit .................................................................... 61
CSRC Bit .................................................................... 61
TRMT Bit .................................................................... 61
TX9 Bit........................................................................ 61
TX9D Bit ..................................................................... 61
TXEN Bit ..................................................................... 61
Address Detect ................................................... 71
Start-up Timer and Power-up Timer ................. 129
(MCLR Not Tied to V
Case 1 ................................................................ 95
Case 2 ................................................................ 95
(MCLR Tied to V
(Master Mode, SREN) ........................................ 75
(Master/Slave) .................................................. 133
PIC16F870/871
DD
) ........................................... 95
DD
)
DD
DS30569B-page 165
) ......................... 96