PIC16F870T-I/SS Microchip Technology, PIC16F870T-I/SS Datasheet - Page 78

• Manufacturer Part Number: PIC16F870T-I/SS
• Description: IC MCU FLASH 2KX14 EE 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F870T-I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• For Use With: I3-DB16F871 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F870/871
9.4
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
9.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 9-10:
DS30569B-page 76
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
19h
8Ch
98h
99h
Legend:
Note 1:
Address
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the
interrupt vector (0004h).
USART Synchronous Slave Mode
x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
USART SYNCHRONOUS SLAVE
TRANSMIT
INTCON
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
USART Transmit Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
GIE
(1)
(1)
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIF
Bit 5
T0IE
CREN ADDEN
SYNC
INTE
Bit 4
TXIF
TXIE
RBIE
Bit 3
—
—
—
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
CCP1IF TMR2IF TMR1IF 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000
BRGH
FERR
Bit 2
T0IF
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
OERR
TRMT
INTF
Bit 1
RX9D
TX9D
Bit 0
R0IF
 2003 Microchip Technology Inc.
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
POR, BOR
Value on:
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
0000 000u
Value on
all other
RESETS