PIC18F65K22-I/MRRSL Microchip Technology, PIC18F65K22-I/MRRSL Datasheet - Page 152

• Manufacturer Part Number: PIC18F65K22-I/MRRSL
• Description: MCU PIC 32K FLASH MEM XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F65K22-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• No. Of I/o's: 53
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F87K22 FAMILY
REGISTER 11-12: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
REGISTER 11-13: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
DS39960B-page 152
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
CCP10IE
TMR5GIE
R/W-0
R/W-0
(1)
CCP10IE:CCP9IE are unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
TMR5GIE: Timer5 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
RC2IE: EUSART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
TX2IE: EUSART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
CTMUIE: CTMU Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP2IE: ECCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP1IE: ECCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP<10:3>IE: CCP<10:3> Interrupt Enable bits
1 = Enabled
0 = Disabled
CCP9IE
R/W-0
R/W-0
—
(1)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
RC2IE
CCP8IE
R/W-0
R-0
CCP7IE
TX2IE
R/W-0
R-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CTMUIE
CCP6IE
R/W-0
R/W-0
(1)
CCP5IE
CCP2IE
R/W-0
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
CCP1IE
CCP4IE
R/W-0
R/W-0
RTCCIE
CCP3IE
R/W-0
R/W-0
bit 0
bit 0