AT32UC3B164-AUT Atmel, AT32UC3B164-AUT Datasheet - Page 54

• Manufacturer Part Number: AT32UC3B164-AUT
• Description: IC MCU AVR32 64KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B164-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Controller Family/series: AT32UC3B
• No. Of I/o's: 28
• Ram Memory Size: 16KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.6.4
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
32059I–06/2010
PLLCOUNT: PLL Count
PLLMUL: PLL Multiply Factor
PLLDIV: PLL Division Factor
PLLOPT: PLL Option
31
23
15
7
-
-
-
-
Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been
These fields determine the ratio of the ouput frequency of the internal VCO of the PLL (f
If PLLOPT[1] bit is set to 0: f
If PLLOPT[1] bit is set to 1: f
Note that the PLLMUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined.
PLLDIV gives also the input frequency of the PLL (f
if the PLLDIV field is set to 0: f
if the PLLDIV field is greater than 0: f
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range.
PLLOPT[1]: Enable the extra output divider.
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).
f
f
VCO
VCO
automatically re-enabled after exiting a sleep mode.
PLL Control Register
= (PLLMUL+1)/(PLLDIV) * f
= 2 * (PLLMUL+1) * f
30
22
14
6
-
-
-
-
PLL0,1
Read/Write
0x020, 0x024
0x00000000
OSC
PLL
PLL
if PLLDIV = 0.
IN
29
21
13
= f
= f
5
-
-
-
= f
OSC
VCO.
VCO
OSC.
if PLLDIV > 0.
IN
/ 2
= f
.
OSC
/ (2 * PLLDIV).
28
20
12
4
-
-
IN
):
PLLOPT
27
19
11
3
PLLCOUNT
26
18
10
2
PLLMUL
PLLDIV
VCO
) to the source oscillator frequency:
PLLOSC
25
17
9
1
AT32UC3B
PLLEN
24
16
8
0
54