AT32UC3B164-AUT Atmel, AT32UC3B164-AUT Datasheet - Page 570
AT32UC3B164-AUT
Manufacturer Part Number
AT32UC3B164-AUT
Description
IC MCU AVR32 64KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Controller Family/series
AT32UC3B
No. Of I/o's
28
Ram Memory Size
16KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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26.5.2
26.5.3
26.6
26.6.1
26.6.2
32059I–06/2010
Functional Description
Clocks
Interrupts
How to Initialize the Module
Data Format
The CLK_ABDAC to the Audio Bitstream DAC is generated by the Power Manager (PM). Before
using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is
enabled in the Power Manager.
The ABDAC needs a separate clock for the D/A conversion operation. This clock,
GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre-
quency must be as follow:
where f
GCLK_ABDAC clock must have a frequency of 12.288MHz.
The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other.
The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC
interrupt requires the interrupt controller to be programmed first.
In order to use the Audio Bitstream DAC the product dependencies given in
page 569
and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.
The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream
DAC Control Register (CR.EN).
The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be
set whenever the ABDAC is ready to receive a new sample. A new sample value should be writ-
ten to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the
Underrun Interrupt Status bit in ISR (ISR.UNDERRUN). ISR is cleared when read, or when writ-
ing one to the corresponding bits in the Interrupt Clear Register (ICR).
The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can
be written to the least and most significant halfword of the Sample Data Register (SDR),
respectively.
An input value of 0x7FFF will result in an output voltage of approximately:
An Input value of 0x8000 will result in an output value of approximately:
s
is the samping rate of the data stream to convert. For f
must be resolved. Particular attention should be given to the configuration of clocks
V
V
OUT
OUT
(
(
0x7FFF
0x8000
)
)
f
GCLK
≈
≈
--------- - VDDIO
128
--------- - VDDIO
128
38
90
=
⋅
⋅
256
×
f
=
=
S
--------- - 3 3
128
--------- - 3 3
128
38
90
⋅
⋅
,
,
≈
≈
0
2
s
,
,
= 48 kHz this means that the
98V
32V
AT32UC3B
Section 26.5 on
570
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