PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 30

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
TABLE 3-2:
DS39616D-page 30
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
V
See the notes following this table for additional
information.
Osc Type
DD
Note 1: Higher
HS
XT
LP
and temperature range for the application.
200 kHz
2: When operating below 3V V
3: Since each resonator/crystal has its own
4: Rs may be required to avoid overdriving
5: Always verify oscillator performance over
32 kHz
1 MHz
stability of oscillator, but also increases
the start-up time.
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
components.
crystals with low drive level specification.
the V
expected for the application.
200 kHz
20 MHz
Crystal
32 kHz
1 MHz
4 MHz
4 MHz
8 MHz
Freq
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
DD
Crystals Used:
and temperature range that is
capacitance
Typical Capacitor Values
values
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
C1
Tested:
20 MHz
4 MHz
8 MHz
increases
of
DD
, or when
33 pF
15 pF
33 pF
27 pF
27 pF
22 pF
15 pF
external
C2
the
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in
FIGURE 3-2:
3.3
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for those concerned with EMI from high-
frequency crystals or users requiring higher clock
speeds from an internal oscillator.
3.3.1
The HSPLL mode uses the HS Oscillator mode for
frequencies up to 10 MHz. A PLL circuit then multiplies
the oscillator output frequency by four to produce an
internal clock frequency up to 40 MHz. The PLLEN bit
is not available in this oscillator mode.
The PLL is only available to the crystal oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (‘0110’).
FIGURE 3-3:
Clock from
Ext. System
OSC2
OSC1
PLL Frequency Multiplier
(from Configuration Register 1H)
HS Mode
HSPLL OSCILLATOR MODE
Crystal
Osc
Open
HS Osc Enable
PLL Enable
F
F
4
IN
OUT
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
PLL BLOCK DIAGRAM
 2010 Microchip Technology Inc.
Comparator
OSC1
OSC2
Loop
Filter
Phase
VCO
PIC18FXXXX
(HS Mode)
Figure
SYSCLK
3-2.