PIC18F4431-E/P Microchip Technology, PIC18F4431-E/P Datasheet - Page 66

• Manufacturer Part Number: PIC18F4431-E/P
• Description: IC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-E/P

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

program memory address embedded into the instruction.
PIC18F2331/2431/4331/4431
6.4
The program memory is addressed in bytes. Instructions
are stored as two bytes or four bytes in program memory.
The Least Significant Byte of an instruction word is
always stored in a program memory location with an
even address (LSB = 0).
how instruction words are stored in the program memory.
To maintain alignment with instruction boundaries, the
PC increments in steps of 2 and the LSB will always read
‘0’.
The CALL and GOTO instructions have the absolute
Since instructions are always stored on word boundaries,
the data contained in the instruction is a word address.
The word address is written to PC<20:1>, which
accesses the desired byte address in program memory.
Instruction 2 in
‘GOTO 000006h’, is encoded in the program memory.
Program branch instructions, which encode a relative
address offset, operate in the same manner. The offset
value stored in a branch instruction represents the num-
ber of single-word instructions that the PC will be offset
by.
further details of the instruction set.
FIGURE 6-5:
EXAMPLE 6-4:
DS39616D-page 66
CASE 1:
Object Code
CASE 2:
Object Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
Section 24.0 “Instruction Set Summary”
Instructions in Program Memory
Figure 6-5
Instruction 1:
Instruction 2:
Instruction 3:
INSTRUCTIONS IN PROGRAM MEMORY
TWO-WORD INSTRUCTIONS
Figure 6-5
shows how the instruction,
Source Code
TSTFSZ
Source Code
MOVFF
ADDWF
TSTFSZ
MOVFF
ADDWF
Program Memory
Byte Locations
MOVLW
GOTO
MOVFF
shows an example of
REG1
REG1, REG2 ; No, skip this word
REG3
REG1
REG1, REG2 ; Yes, execute this word
REG3
055h
000006h
123h, 456h
provides


; is RAM location 0?
; Execute this word as a NOP
; continue code
; is RAM location 0?
; 2nd word of instruction
; continue code
LSB = 1
6.4.1
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the four MSbs of an instruction
specifies a special form of NOP. If the instruction is exe-
cuted in proper sequence, immediately after the first
word, the data in the second word is accessed and
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC.
EFh
C1h
0Fh
F0h
F4h
Note:
Example 6-4
TWO-WORD INSTRUCTIONS
For information on two-word instructions
in the extended instruction set, see
Section 24.2 “Instruction
LSB = 0
55h
03h
00h
23h
56h
shows how this works.
Word Address
 2010 Microchip Technology Inc.
00000Ah
00000Ch
00000Eh
000000h
000002h
000004h
000006h
000008h
000010h
000012h
000014h

Set”.