DSPIC33FJ64GP204-I/PT Microchip Technology, DSPIC33FJ64GP204-I/PT Datasheet
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... Microchip Technology Inc. Data Sheet High-Performance, 16-bit Digital Signal Controllers Preliminary DS70292B ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA © 2008 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Timers/Capture/Compare/PWM: • Timer/Counters five 16-bit timers: ...
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... Programmable bit length for the CRC generator polynomial (up to 16-bit length) - 8-deep, 16-bit or 16-deep, 8-bit FIFO for data input Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: See the device variant tables for exact peripheral features per device. Preliminary © 2008 Microchip Technology Inc. ...
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... Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32GP302/304, which include 1 Kbyte of DMA RAM. 2: Only four out of five timers are remappable. 3: Only two out of three interrupts are remappable. ...
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... AN11/RP13 5 24 (1) AN12/RP12 6 23 PGC2/EMUC2/TMS/RP11 PGD2/EMUD2/TDI/RP10 CAP DDCORE TDO/SDA1/RP9 11 18 TCK/SCL1/RP8 12 17 (1) V INT0/RP7 /CN23/PMD5/RB7 PGC3/EMUC3/ASCL1/RP6 14 15 Preliminary (1) /CN11/PMCS1/RB15 (1) /CN12/PMWR/RB14 (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 (1) /CN21/PMD3/RB9 (1) /CN22/PMD4/RB8 (1) /CN24/PMD6/RB6 /CN11/PMCS1/RB15 (1) /CN12/PMWR/RB14 /CN13/PMRD/RB13 /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 (1) /CN21/PMD3/RB9 (1) /CN22/PMD4/RB8 (1) /CN24/PMD6/RB6 © 2008 Microchip Technology Inc. ...
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... AN5/C1IN+/RP3 /CN7/RB3 V OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. © 2008 Microchip Technology Inc. AN11/DAC1RN/RP13 1 21 AN12/DAC1RP/RP12 2 20 PGC2/EMUC2/TMS/RP11 ...
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... The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. DS70292B-page 6 AN11/RP13 1 21 AN12/RP12 2 20 dsPIC33FJ32GP302 PGC2/EMUC2/TMS/RP11 3 19 dsPIC33FJ64GP202 PGD2/EMUD2/TDI/RP10 4 18 dsPIC33FJ128GP202 CAP TDO/SDA1/RP9 15 Preliminary (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 DDCORE (1) /CN21/PMD3/RB9 © 2008 Microchip Technology Inc. ...
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... OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. © 2008 Microchip Technology Inc. AN11/DAC1RN/RP13 11 23 AN12/DAC1RP/RP12 24 10 PGC2/EMUC2/RP11 25 ...
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... The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. DS70292B-page 8 AN11/RP13 11 23 AN12/RP12 24 10 PGC2/EMUC2/RP11 25 9 PGD2/EMUD2/RP10 26 8 dsPIC33FJ32GP304 V /V CAP 27 7 dsPIC33FJ64GP204 (1) RP25 dsPIC33FJ128GP204 29 5 (1) RP24 30 4 (1) RP23 31 3 (1) RP22 32 ...
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... V SS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. © 2008 Microchip Technology Inc. 11 AN11/DAC1RN/RP13 AN12/DAC1RP/RP12 25 9 PGC2/EMUC2/RP11 8 ...
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... The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals. DS70292B-page 10 11 AN11/RP13 AN12/RP12 25 9 PGC2/EMUC2/RP11 8 26 PGD2/EMCD2/RP10 dsPIC33FJ32GP304 CAP DDCORE 6 dsPIC33FJ64GP204 ( RP25 /CN19/PMA6/RC9 dsPIC33FJ128GP204 (1) 4 RP24 /CN20/PMA5/RC8 30 3 (1) RP23 /CN17/PMA0/RC7 31 (1) 2 RP22 ...
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... Electrical Characteristics .......................................................................................................................................................... 309 30.0 Packaging Information.............................................................................................................................................................. 355 Appendix A: Revision History............................................................................................................................................................. 365 Index .................................................................................................................................................................................................. 367 The Microchip Web Site ..................................................................................................................................................................... 373 Customer Change Notification Service .............................................................................................................................................. 373 Customer Support .............................................................................................................................................................................. 373 Reader Response .............................................................................................................................................................................. 374 Product Identification System ............................................................................................................................................................ 375 © 2008 Microchip Technology Inc. Preliminary DS70292B-page 11 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS70292B-page 12 Preliminary © 2008 Microchip Technology Inc. ...
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... Family Reference Manual, which is available from the Microchip website (www.microchip.com) © 2008 Microchip Technology Inc. This document contains device specific information for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Digital Signal Controller (DSC) Devices. The dsPIC33F devices ...
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... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support MCLR Timers UART1, 2 ADC1 1-5 IC1 CNx I2C1 Preliminary PORTA DMA RAM PORTB 16 DMA Controller PORTC Remappable Pins 16-bit ALU 16 OC/ PWM1-4 DCI © 2008 Microchip Technology Inc. ...
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... ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer © 2008 Microchip Technology Inc. Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input O = Output Preliminary P = Power I = Input © 2008 Microchip Technology Inc. ...
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... A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the dsPIC33FJ32GP302/ 304, dsPIC33FJ64GPX02/X04, dsPIC33FJ128GPX02/X04 is shown in Figure 2-2. © 2008 Microchip Technology Inc. 2.2 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory ...
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... PCH PCL X RAM Y RAM Address Loop Address Latch Control Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2008 Microchip Technology Inc. ...
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... Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2008 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 PC0 0 Program Space Visibility Page Address ...
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... This bit can be read or cleared (not set). Clearing this bit clears SA and SB. DS70292B-page 20 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) (4) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2008 Microchip Technology Inc. ...
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... Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). 4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. © 2008 Microchip Technology Inc. (2) Preliminary DS70292B-page 21 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70292B-page 22 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2008 Microchip Technology Inc. ...
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... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2008 Microchip Technology Inc. Preliminary DS70292B-page 23 ...
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... Automatic saturation on/off for ACCA (SATA) • Automatic saturation on/off for ACCB (SATB) • Automatic saturation on/off for writes to data memory (SATDW) • Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 2-3. Preliminary © 2008 Microchip Technology Inc. ...
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... Instruction CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2008 Microchip Technology Inc. Algebraic Operation – y – y • change • – x • – x • y 40-bit Accumulator A 40-bit Accumulator B Saturate Adder ...
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... If the COVTE bit in the INTCON1 register is set, the SA and SB bits generate an arithmetic warning trap when saturation is disabled. Preliminary previously and the SAT<A:B> warning trap when set and © 2008 Microchip Technology Inc. the ...
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... The rounded contents of the non-target accumu- lator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). © 2008 Microchip Technology Inc. 2.7.3.1 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store) ...
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... DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. Preliminary © 2008 Microchip Technology Inc. ...
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... Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) Reserved Note: Memory areas are not shown to scale. © 2008 Microchip Technology Inc. 3.1 Program Address Space The program dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 and instructions. The space is addressable by a 24-bit families ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2008 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2008 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... SFR Space 0x07FF 0x0801 X Data RAM (X) 0x0FFF 0x1001 Y Data RAM (Y) 0x13FF 0x1401 DMA RAM 0x17FF 0x1801 0x8001 X Data Unimplemented (X) Preliminary LSb Address 0x0000 0x07FE 0x0800 6 Kbyte 0x0FFE Near 0x1000 Data Space 0x13FE 0x1400 0x17FE 0x1800 0x8000 0xFFFE © 2008 Microchip Technology Inc. ...
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... Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2008 Microchip Technology Inc. LSb 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 ...
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... Program Memory 0xFFFF DS70292B-page 34 LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x47FE 0x4800 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2008 Microchip Technology Inc. ...
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... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2008 Microchip Technology Inc. 3.2.6 DMA RAM Every dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ ...
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... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary © 2008 Microchip Technology Inc. addressing modes are ...
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... Not all instructions support all the address- ing modes given above. Individual instruc- tions may support different subsets of these addressing modes. © 2008 Microchip Technology Inc. Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
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... W1, X AGU for modulo MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary between the © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment If the length of a bit-reversed buffer the last ‘ ...
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... TABLE 3-38: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address DS70292B-page 58 Bit-Reversed Address Decimal Preliminary A0 Decimal © 2008 Microchip Technology Inc. ...
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... Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2008 Microchip Technology Inc. 3.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
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... Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70292B-page 60 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2008 Microchip Technology Inc. ...
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... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2008 Microchip Technology Inc Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
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... Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2008 Microchip Technology Inc. ...
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... Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2008 Microchip Technology Inc. controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and and TBLWT (table write) instructions. With RTSP, the user ...
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... Flash in RTSP mode. A programming operation is nominally duration and the processor stalls (waits) until the operation is (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. required for Preliminary finished. Setting the WR bit © 2008 Microchip Technology Inc. ...
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... Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2008 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70292B-page 66 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2008 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2008 Microchip Technology Inc. ...
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... V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2008 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure 5-1. Any active source of reset will make the SYSRST sig- nal active. On system Reset, some of the registers and associated with the CPU and peripherals are forced to ...
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... SWDTEN bit setting. DS70292B-page 70 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2008 Microchip Technology Inc. (1) (CONTINUED) Preliminary ...
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... BOR BOR ) after a PWRT ensures that the system PWRT for more FSCM Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2008 Microchip Technology Inc. ...
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... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2008 Microchip Technology Inc. Vbor V BOR ...
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... Power-up timer (PWRT) is too low DD ) for proper device operation. The BOR cir- crosses V DD has elapsed. The delay BOR ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT trip point BOR © 2008 Microchip Technology Inc. BOR DD ...
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... Reset state. This Reset state will not re-initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will com- mence. © 2008 Microchip Technology Inc BOR PWRT ...
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... Illegal opcode or uninitialized W register access or Security Reset Configuration Mismatch MCLR Reset RESET instruction WDT time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction POR, BOR POR Preliminary Cleared by: POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR © 2008 Microchip Technology Inc. ...
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... These are summarized in Table 6-1. © 2008 Microchip Technology Inc. 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the ...
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... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70292B-page 78 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2008 Microchip Technology Inc. ...
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... Microchip Technology Inc. AIVT Address 0x000104 Reserved 0x000106 Oscillator Failure 0x000108 Address Error 0x00010A Stack Error 0x00010C Math Error 0x00010E DMA Error 0x000110 Reserved 0x000112 Reserved 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – ...
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... C1TX – ECAN1 TX Data Request 0x0001A2 Reserved 0x0001A4 Reserved 0x0001A6 Reserved 0x0001A8 Reserved 0x0001AA Reserved 0x0001AC Reserved 0x0001AE Reserved 0x0001B0 DAC1R – DAC1 Right Data Request 0x0001B2 DAC1L – DAC1 Left Data Request 0x0001B4-0x0001FE Reserved Preliminary Interrupt Source © 2008 Microchip Technology Inc. ...
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... IEC X The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2008 Microchip Technology Inc. 6.3.4 IPC X The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
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... IPL<3> The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15> DS70292B-page 82 (1) R/C-0 R-0 SB OAB (3) R-0 R/W-0 ( Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2008 Microchip Technology Inc. ...
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... CPU interrupt priority level is greater than CPU interrupt priority level less Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2008 Microchip Technology Inc. (1) R/W-0 R/W-0 ...
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... Math error trap has not occurred DS70292B-page 84 R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OVBTE COVTE bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. Preliminary DS70292B-page 85 ...
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... Interrupt on positive edge DS70292B-page 86 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...
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... DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70292B-page 88 Preliminary © 2008 Microchip Technology Inc. ...
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... INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF ...
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... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70292B-page 90 Preliminary © 2008 Microchip Technology Inc. ...
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... Interrupt request has not occurred bit 0 SPI2EIF: SPI2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Note 1: Interrupts disabled on devices without ECAN™ modules © 2008 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
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... Unimplemented: Read as ‘0’ DS70292B-page 92 R/W-0 R/W-0 U-0 DCIIF DCIEIF — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 95
... U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts disabled on devices without ECAN™ modules. 2: Interrupts disabled on devices without Audio DAC modules. © 2008 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 96
... Interrupt request not enabled DS70292B-page 94 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 R/W-0 R/W-0 DMA0IE T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 97
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008 Microchip Technology Inc. Preliminary DS70292B-page 95 ...
Page 98
... Interrupt request not enabled DS70292B-page 96 R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 R/W-0 INT1IE CNIE CMIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IE DMA2IE bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 99
... Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008 Microchip Technology Inc. Preliminary DS70292B-page 97 ...
Page 100
... U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) (1) DMA3IE C1IE C1RXIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SPI2IE SPI2EIE bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 101
... DCIIE: DCI Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 DCIEIE: DCI Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. R/W-0 R/W-0 U-0 DCIIE DCIEIE — U-0 U-0 U-0 — ...
Page 102
... DS70292B-page 100 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DMA6IE CRCIE U2EIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) (1) Preliminary U-0 U-0 — — bit 8 R/W-0 U-0 U1EIE — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 103
... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 104
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292B-page 102 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC2IP<2:0> bit 8 R/W-0 R/W-0 DMA0IP<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 105
... Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 106
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292B-page 104 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 DMA1IP<2:0> bit 8 R/W-0 R/W-0 U1TXIP<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 107
... Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 108
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292B-page 106 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 IC7IP<2:0> bit 8 R/W-0 R/W-0 INT1IP<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 109
... Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 110
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292B-page 108 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2RXIP<2:0> bit 8 R/W-0 R/W-0 T5IP<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 111
... SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Interrupts disabled on devices without ECAN™ modules © 2008 Microchip Technology Inc. R/W-0 U-0 R/W-1 (1) — R/W-0 U-0 R/W-1 — ...
Page 112
... Interrupt source is disabled DS70292B-page 110 U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 DMA3IP<2:0> bit Bit is unknown ...
Page 113
... PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 114
... Unimplemented: Read as ‘0’ DS70292B-page 112 R/W-0 U-0 U-0 — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 115
... Interrupt source is disabled bit 3-0 DCIIP<2:0>: DCI Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2008 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 116
... Unimplemented: Read as ‘0’ DS70292B-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 U2EIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 117
... DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled Note 1: Interrupts disabled on devices without ECAN™ modules © 2008 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 118
... Note 1: Interrupts disabled on devices without Audio DAC modules. DS70292B-page 116 R/W-0 U-0 R/W-0 (1) — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 (1) DAC1RIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 119
... Unimplemented: Read as ‘0’ bit 6-0 VECNUM: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2008 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
Page 120
... Only user interrupts with a priority level lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2008 Microchip Technology Inc. ...
Page 121
... ECAN1 – TX Data Request DCI – Codec Transfer Done DAC1 – Right Data Output DAC2 – Left Data Output © 2008 Microchip Technology Inc. Direct Memory Access (DMA very efficient mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), ...
Page 122
... Alternatively, an interrupt can be generated when half of the block has been filled. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus Preliminary DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2008 Microchip Technology Inc. ...
Page 123
... DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write colli- sion flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. © 2008 Microchip Technology Inc. The DMAxCON, DMAxREQ, DMAxCNT are all conventional read/write registers. ...
Page 124
... Continuous, Ping-Pong modes disabled DS70292B-page 122 R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 125
... DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 6-1 for a complete listing of IRQ numbers for all interrupt sources. © 2008 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 126
... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 127
... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> ...
Page 128
... DS70292B-page 126 R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 129
... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2008 Microchip Technology Inc. Preliminary DS70292B-page 127 ...
Page 130
... DMA0STA register selected DS70292B-page 128 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 131
... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2008 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...
Page 132
... NOTES: DS70292B-page 130 Preliminary © 2008 Microchip Technology Inc. ...
Page 133
... SOSCO LPOSCEN SOSCI Auxiliary Oscillator Note 1: See Figure 8-2 for PLL details. © 2008 Microchip Technology Inc. • An on-chip Phase-Locked Loop (PLL) to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed ...
Page 134
... MHz. The crystal is connected to the SOSCI and SOSCO pins. External Clock (EC): External clock signal Mhz. The external clock signal is directly applied to SOSCI pin. Preliminary Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> is divided OSC ). F CY MHz are supported given by: DEVICE OPERATING FREQUENCY OSC © 2008 Microchip Technology Inc. CY the ...
Page 135
... FIGURE 8-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) © 2008 Microchip Technology Inc. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F EQUATION 8-2: For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. • ...
Page 136
... This is the default oscillator mode for an unprogrammed (erased) device. DS70292B-page 134 Oscillator Source POSCMD<1:0> Internal xx Internal xx Internal xx Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx Preliminary FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 011 011 1 011 010 010 1 010 1 001 1 000 © 2008 Microchip Technology Inc. ...
Page 137
... Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clear by application FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. R-0 U-0 R/W-y — U-0 R/C-0 U-0 — ...
Page 138
... OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete DS70292B-page 136 Preliminary © 2008 Microchip Technology Inc. ...
Page 139
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...
Page 140
... DS70292B-page 138 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 141
... Center frequency +0.375% (7.40 MHz) 000000 = Center frequency (7.37 MHz nominal) 111111 = Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) © 2008 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 142
... Unimplemented: Read as ‘0’ DS70292B-page 140 R/W-0 R/W-0 R/W-0 AOSCMD<1:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 APSTSCLR<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 143
... Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. © 2008 Microchip Technology Inc. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits ...
Page 144
... NOTES: DS70292B-page 142 Preliminary © 2008 Microchip Technology Inc. ...
Page 145
... Configuration”. EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2008 Microchip Technology Inc. 9.2 Instruction-Based Power-Saving Modes dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices have two and ...
Page 146
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible ® DSC © 2008 Microchip Technology Inc. ...
Page 147
... WR Port Data Latch Read LAT Read Port © 2008 Microchip Technology Inc. peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. When a peripheral is enabled and the peripheral is ...
Page 148
... Typically this instruction would be an NOP, as shown in Example 10- Preliminary (e.g., 5V) on any desired DD specification. IH Digital Only/5V Tolerant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes © 2008 Microchip Technology Inc. ...
Page 149
... Delay 1 cycle btss PORTB, #13 ; Next Instruction © 2008 Microchip Technology Inc. Each CN pin also has a weak pull-up connected to it. The pull-ups act as a current source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The ...
Page 150
... Figure 10-2 Illustrates remappable pin selection for U1RX input. FIGURE 10-2: REMAPPABLE MUX INPUT FOR U1RX RP0 RP1 RP2 RP 25 Preliminary © 2008 Microchip Technology Inc. Programming a given U1RXR<4:0> U1RX input to peripheral 2 25 ...
Page 151
... SPI2 Slave Select Input DCI Serial Data Input DCI Serial Clock Input DCI Frame Sync Input ECAN1 Receive Note 1: Unless otherwise noted, all inputs use Schmitt input buffers. © 2008 Microchip Technology Inc. Function Name Register INT1 RPINR0 INT2 RPINR1 T2CK ...
Page 152
... RPn tied to Output Compare 2 10011 RPn tied to Output Compare 3 10100 RPn tied to Output Compare 4 10101 Preliminary MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPn RPnR<4:0> default 0 3 Output Enable OC4 Output 21 default 0 U1TX Output 3 RPn Output Data OC4 Output 21 Output Name © 2008 Microchip Technology Inc. ...
Page 153
... Microchip Technology Inc. 10.4.3.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers ...
Page 154
... IOLOCK bit to ‘0’. See Register R/W-1 R/W-1 INT1R<4:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 155
... INTR2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 INT2R<4:0> Unimplemented bit, read as ‘0’ ...
Page 156
... Input tied to RP1 00000 = Input tied to RP0 DS70292B-page 154 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 157
... T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as ‘0’ ...
Page 158
... Input tied to RP1 00000 = Input tied to RP0 DS70292B-page 156 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 159
... IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ...
Page 160
... Input tied to RP0 DS70292B-page 158 U-0 U-0 — — R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 161
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ...
Page 162
... Input tied to RP1 00000 = Input tied to RP0 DS70292B-page 160 R/W-1 R/W-1 U2CTSR<4:0> R/W-1 R/W-1 U2RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 163
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 164
... Input tied to RP0 DS70292B-page 162 U-0 U-0 — — R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 165
... SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. R/W-1 R/W-1 SCK2R<4:0> R/W-1 R/W-1 SDI2R<4:0> Unimplemented bit, read as ‘0’ ...
Page 166
... Input tied to RP0 DS70292B-page 164 U-0 U-0 — — R/W-1 R/W-1 SS2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 167
... CSDIR<4:0>: Assign DCI Serial Data Input (CSDI) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2008 Microchip Technology Inc. R/W-1 R/W-1 CSCKR<4:0> R/W-1 R/W-1 CSDIR<4:0> Unimplemented bit, read as ‘0’ ...
Page 168
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown (1) U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 169
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-3 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-3 for peripheral function numbers) © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...
Page 170
... Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
Page 171
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-3 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-3 for peripheral function numbers) © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...
Page 172
... Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 10-3 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 ...
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... Bit is cleared R/W-0 R/W-0 R/W-0 RP23R<4:0> R/W-0 R/W-0 R/W-0 RP22R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 10-3 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2008 Microchip Technology Inc. (1) R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 ...
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... NOTES: DS70292B-page 174 Preliminary © 2008 Microchip Technology Inc. ...
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... TCKPS<1:0> SOSCI (1) LPOSCEN Note 1: Refer to Section 8.0 “Oscillator Configuration” for information on enabling the secondary oscillator. © 2008 Microchip Technology Inc. The Timer1 module can operate in one of the following modes: • Timer mode • Gated Timer mode and • Synchronous Counter mode ...
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... DS70292B-page 176 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Prescaler F CY TCKPS<1:0> Prescaler Sync TxCK TCKPS<1:0> © 2008 Microchip Technology Inc. • The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. A block diagram of the Type B timer is shown in and Figure 12-1. ...
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... The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. Preliminary 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 © 2008 Microchip Technology Inc. ...
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... F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers 2: Timer Type B Timer ( and 4) 3: Timer Type C Timer ( and 5) © 2008 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw TMRx TMRy 00 x1 TMRyHLD ...
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... DS70292B-page 180 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /2) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits have no effect. © 2008 Microchip Technology Inc. U-0 U-0 (1) — ...
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... NOTES: DS70292B-page 182 Preliminary © 2008 Microchip Technology Inc. ...
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... Falling Edge Mode Edge Detection Mode Sleep/Idle Wake-up Mode Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2008 Microchip Technology Inc. 2. Capture timer value on every edge (rising and falling) 3. Prescaler Capture Event modes: - Capture timer value on every 4th rising edge ...
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... Input capture module turned off DS70292B-page 184 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2008 Microchip Technology Inc. ...
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... TMR3 TMR2 © 2008 Microchip Technology Inc. The state of the output pin changes when the timer value matches the compare register value. The Output Compare module generates either a single output pulse or a sequence of output pulses, by changing the and state of the output pin on the compare match events. ...
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... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match Preliminary — © 2008 Microchip Technology Inc. ...
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... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2008 Microchip Technology Inc. U-0 U-0 U-0 — ...
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... NOTES: DS70292B-page 188 Preliminary © 2008 Microchip Technology Inc. ...
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... SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF © 2008 Microchip Technology Inc. peripheral devices can be serial EEPROMs, shift regis- ters, display drivers, analog-to-digital converters, etc. The SPI module is compatible with SPI and SIOP from ® Motorola . Each SPI module consists of a 16-bit shift register, ...
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... DS70292B-page 190 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2008 Microchip Technology Inc. U-0 U-0 — — bit 8 R-0 R-0 SPITBF SPIRBF bit Bit is unknown ...
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... MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2008 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 DISSCK DISSDO ...
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... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70292B-page 192 Preliminary © 2008 Microchip Technology Inc. ...
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... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2008 Microchip Technology Inc. U-0 U-0 U-0 — ...
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... NOTES: DS70292B-page 194 Preliminary © 2008 Microchip Technology Inc. ...
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... For details about the communication sequence in each of these modes, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F Family Reference Manual chapters. © 2008 Microchip Technology Inc Registers I2CxCON and I2CxSTAT are control and status registers, respectively ...
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... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2008 Microchip Technology Inc. ...
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... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2008 Microchip Technology Inc. R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
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... Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence Start condition not in progress DS70292B-page 198 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte master master) Preliminary 2 C master) © 2008 Microchip Technology Inc. ...