DSPIC33FJ64GP204-I/PT Microchip Technology, DSPIC33FJ64GP204-I/PT Datasheet - Page 281

IC DSPIC MCU/DSP 64K 44-TQFP

DSPIC33FJ64GP204-I/PT

Manufacturer Part Number
DSPIC33FJ64GP204-I/PT
Description
IC DSPIC MCU/DSP 64K 44-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP204-I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Core Frequency
40MHz
Embedded Interface Type
ECAN, I2C, SPI, UART
No. Of I/o's
35
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ64GP204-I/PT
Manufacturer:
ST
Quantity:
101
Part Number:
DSPIC33FJ64GP204-I/PT
Manufacturer:
MICROCHIP
Quantity:
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Part Number:
DSPIC33FJ64GP204-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
25.0
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable.
FIGURE 25-1:
© 2008 Microchip Technology Inc.
Note:
Parallel Master Port
Note 1: 28-pin devices do not have PMA<10:2>.
PARALLEL MASTER PORT
(PMP)
dsPIC33F
This data sheet summarizes the features
of
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04
devices. It is not intended to be a
comprehensive reference source.
complement the information in this data
sheet, refer to the dsPIC33F Family
Reference
Parallel Master Port (PMP)”, which is
available from the Microchip website
(www.microchip.com).
the
PMP MODULE OVERVIEW
Manual,
dsPIC33FJ32GP302/304,
“Section
families
PMA<0>
PMALL
PMA<1>
PMALH
PMA<10:2>
PMCS1
PMBE
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMA<7:0>
PMA<15:8>
PMA<14>
and
35.
Preliminary
To
(1)
of
Microcontroller
Key features of the PMP module include:
• Fully multiplexed address/data mode
• Demultiplexed or partially multiplexed address/
• One Chip Select Line
• Programmable Strobe Options
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
• Programmable Wait States
• Selectable Input Voltage Levels
data mode
- up to 11 address lines with single chip select
- up to 12 address lines without chip select
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
- Address Support
- 4-Byte Deep Auto-Incrementing Buffer
Up to 11-Bit Address
8-Bit Data
LCD
Address Bus
Data Bus
Control Lines
Buffer
FIFO
DS70292B-page 279
EEPROM

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