DSPIC33FJ64GP204-I/PT Microchip Technology, DSPIC33FJ64GP204-I/PT Datasheet - Page 75

IC DSPIC MCU/DSP 64K 44-TQFP

DSPIC33FJ64GP204-I/PT

Manufacturer Part Number
DSPIC33FJ64GP204-I/PT
Description
IC DSPIC MCU/DSP 64K 44-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ64GP204-I/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Core Frequency
40MHz
Embedded Interface Type
ECAN, I2C, SPI, UART
No. Of I/o's
35
Flash Memory Size
64KB
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ64GP204-I/PT
Manufacturer:
ST
Quantity:
101
Part Number:
DSPIC33FJ64GP204-I/PT
Manufacturer:
MICROCHIP
Quantity:
390
Part Number:
DSPIC33FJ64GP204-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
FIGURE 5-2:
© 2008 Microchip Technology Inc.
Oscillator Clock
Device Status
POR Reset
BOR Reset
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
SYSRST
FSCM
V
DD
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
6: The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is
active until V
the V
becomes stable.
period of time (T
at the appropriate level for full-speed operation. After the delay T
inactive, which in turn enables the selected oscillator to start generating clock cycles.
Table 5-1. Refer to Section 8.0 “Oscillator Configuration” for more information.
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
ready and the delay T
1
SYSTEM RESET TIMING
BOR
2
threshold and the delay T
DD
T
crosses the V
PWRT
V
POR
POR
) after a BOR. The delay T
FSCM
elapsed.
POR
threshold and the delay T
Preliminary
Vbor
V
BOR
BOR
has elapsed. The delay T
T
PWRT
T
3
BOR
Reset
Time
PWRT
ensures that the system power supplies have stabilized
T
OSCD
POR
has elapsed.
PWRT
BOR
T
OST
4
ensures the voltage regulator output
has elapsed, the SYSRST becomes
T
LOCK
DS70292B-page 73
5
6
Run
DD
T
FSCM
crosses

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