ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 134
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ATMEGA32U4-MU
Manufacturer Part Number
ATMEGA32U4-MU
Description
MCU AVR 32K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U4-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Interface Type
EBI/I2S/SPI/TWI/USART/USB
On-chip Adc
12-chx10-bit
Number Of Timers
5
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16MU
ATMEGA32U4-16MU
ATMEGA32U4-16MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
- Current page: 134 of 433
- Download datasheet (9Mb)
14.10.7
14.10.8
14.10.9
14.10.10 Output Compare Register 1 B – OCR1BH and OCR1BL
14.10.11 Output Compare Register 1 C – OCR1CH and OCR1CL
7766F–AVR–11/10
Timer/Counter1 – TCNT1H and TCNT1L
Timer/Counter3 – TCNT3H and TCNT3L
Output Compare Register 1 A – OCR1AH and OCR1AL
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 110.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
TCNT1[15:8]
TCNT1[7:0]
R/W
0
7
TCNT3[15:8]
TCNT3[7:0]
R/W
0
7
R/W
0
7
R/W
0
7
R/W
0
6
R/W
0
6
R/W
0
6
R/W
0
6
R/W
0
6
R/W
0
5
R/W
0
5
R/W
0
5
R/W
0
5
R/W
0
5
R/W
0
4
R/W
0
4
R/W
0
4
R/W
0
4
R/W
0
4
R/W
0
OCR1A[15:8]
OCR1B[15:8]
OCR1C[15:8]
OCR1A[7:0]
OCR1B[7:0]
OCR1C[7:0]
3
0
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
R/W
2
R/W
0
2
R/W
0
2
R/W
0
2
R/W
0
2
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
1
R/W
0
ATmega16/32U4
0
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
0
R/W
0
See “Accessing 16-bit
TCNT1H
TCNT1L
TCNT3H
TCNT3L
OCR1AH
OCR1AL
OCR1BH
OCR1BL
OCR1CH
OCR1CL
134
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