ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 53
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATMEGA32U4-MU
Manufacturer Part Number
ATMEGA32U4-MU
Description
MCU AVR 32K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U4-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Interface Type
EBI/I2S/SPI/TWI/USART/USB
On-chip Adc
12-chx10-bit
Number Of Timers
5
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16MU
ATMEGA32U4-16MU
ATMEGA32U4-16MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
- Current page: 53 of 433
- Download datasheet (9Mb)
8.0.6
8.0.7
8.0.8
7766F–AVR–11/10
Watchdog Reset
USB Reset
MCU Status Register – MCUSR
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
page 55
Figure 8-6.
When the USB controller is enabled and configured with the USB Reset CPU feature enabled
and if a valid USB Reset signalling is detected on the bus, the CPU core is reset but the USB
controller remains enabled and attached. This feature may be used to enhance device reliability.
Figure 8-7.
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 7..6 - Reserved
These bits are reserved and should be read as 0. Do not set these bits.
Bit
Read/Write
Initial Value
for details on operation of the Watchdog Timer.
CC
DM
DP
CC
7
–
R
0
Watchdog Reset During Operation
USB Reset During Operation
6
–
R
0
USB Traffic
5
USBRF
R
0
CK
4
JTRF
R/W
See Bit Description
3
WDRF
R/W
2
BORF
R/W
End of Reset
1
EXTRF
R/W
ATmega16/32U4
USB Traffic
0
PORF
R/W
MCUSR
TOUT
. Refer to
53
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