ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 284
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ATMEGA32U4-MU
Manufacturer Part Number
ATMEGA32U4-MU
Description
MCU AVR 32K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U4-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Interface Type
EBI/I2S/SPI/TWI/USART/USB
On-chip Adc
12-chx10-bit
Number Of Timers
5
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16MU
ATMEGA32U4-16MU
ATMEGA32U4-16MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
- Current page: 284 of 433
- Download datasheet (9Mb)
ATmega16/32U4
• 7 - CFGOK - Configuration Status Flag
Set by hardware when the endpoint X size parameter (EPSIZE) and the bank parametrization
(EPBK) are correct compared to the max FIFO capacity and the max number of allowed bank.
This bit is updated when the bit ALLOC is set.
If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and
EPBK values.
• 6 - OVERFI - Overflow Error Interrupt Flag
Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 22.15, page 275 for more details.
Shall be cleared by software. Setting by software has no effect.
• 5 - UNDERFI - Flow Error Interrupt Flag
Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 22.15, page 275 for more details.
Shall be cleared by software. Setting by software has no effect.
• 4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - DTSEQ1:0 - Data Toggle Sequencing Flag
Set by hardware to indicate the PID data of the current bank:
00b Data0
01b Data1
1xb
Reserved.
For OUT transfer, this value indicates the last data toggle received on the current bank.
For IN transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not
relative to the current bank.
• 1-0 - NBUSYBK1:0 - Busy Bank Flag
Set by hardware to indicate the number of busy bank.
For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer.
For OUT endpoint, it indicates the number of busy bank(s) filled by OUT transaction from the
host.
00b All banks are free
01b 1 busy bank
10b 2 busy banks
11b Reserved.
284
7766F–AVR–11/10
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