ATMEGA32U4-MU Atmel, ATMEGA32U4-MU Datasheet - Page 146
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ATMEGA32U4-MU
Manufacturer Part Number
ATMEGA32U4-MU
Description
MCU AVR 32K FLASH 16MHZ 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U4-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN
Package
44QFN EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Interface Type
EBI/I2S/SPI/TWI/USART/USB
On-chip Adc
12-chx10-bit
Number Of Timers
5
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA32U4-16MU
ATMEGA32U4-16MU
ATMEGA32U4-16MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32U4-MUR
Manufacturer:
UCC
Quantity:
1 001
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- Download datasheet (9Mb)
15.6
7766F–AVR–11/10
Compare Match Output Unit
The length of the counting period is user adjustable by selecting the dead time prescaler setting
by using the DTPS41:40 control bits, and selecting then the dead time value in I/O register DT4.
The DT4 register consists of two 4-bit fields, DT4H and DT4L that control the dead time periods
of the PWM output and its' complementary output separately in terms of the number of pres-
caled dead time generator clock cycles. Thus the rising edge of OC4x and OC4x can have
different dead time periods as the t
t
Figure 15-8. The Complementary Output Pair, COM4x1:0 = 1
OCWnx
OCnx
OCnx
(COMnx = 1)
The Compare Output Mode (COM4x1:0) bits have two functions. The Waveform Generator uses
the COM4x1:0 bits for defining the inverted or non-inverted Waveform Output (OCW4x) at the
next Compare Match. Also, the COM4x1:0 bits control the OC4x and OC4x pin output source.
Figure 15-9
I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general
I/O Port Control Registers (DDR and PORT) that are affected by the COM4x1:0 bits are shown.
In Normal Mode (non-PWM) the Dead Time Generator is disabled and it is working like a syn-
chronizer: the Output Compare (OC4x) is delayed from the Waveform Output (OCW4x) by one
timer clock cycle. Whereas in Fast PWM Mode and in Phase and Frequency Correct PWM
Mode when the COM4x1:0 bits are set to “01” both the non-inverted and the inverted Output
Compare output are generated, and an user programmable Dead Time delay is inserted for
these complementary output pairs (OC4x and OC4x). The functionality in PWM modes is similar
to Normal mode when any other COM4x1:0 bit setup is used. When referring to the OC4x state,
the reference is for the Output Compare output (OC4x) from the Dead Time Generator, not the
OC4x pin. If a system reset occur, the OC4x is reset to “0”.
The general I/O port function is overridden by the Output Compare (OC4x / OC4x) from the
Dead Time Generator if either of the COM4x1:0 bits are set. However, the OC4x pin direction
(input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data
Direction Register bit for the OC4x and OC4x pins (DDR_OC4x and DDR_OC4x) must be set as
output before the OC4x and OC4x values are visible on the pin. The port override function is
independent of the Output Compare mode.
The design of the Output Compare Pin Configuration logic allows initialization of the OC4x state
before the output is enabled. Note that some COM4x1:0 bit settings are reserved for certain
modes of operation. For Output Compare Pin Configurations refer to
Table 15-3 on page
non-overlap / falling edge
t
non-overlap / rising edge
shows a simplified schematic of the logic affected by the COM4x1:0 bit setting. The
is adjusted by the 4-bit DT4L value.
152,
Table 15-4 on page
t
non-overlap / falling edge
non-overlap / rising edge
154, and
is adjusted by the 4-bit DT4H value and the
Table 15-5 on page
ATmega16/32U4
Table 15-2 on page
155.
151,
146
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