AT32UC3B0256-A2UR Atmel, AT32UC3B0256-A2UR Datasheet - Page 395

• Manufacturer Part Number: AT32UC3B0256-A2UR
• Description: MCU AVR32 256K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-A2UR

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Package: 64TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 44
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32059K–03/2011
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt
Clear (TXOUTIC) bit in UPCONnCLR) to acknowledge the interrupt, what has no effect on the
pipe FIFO.
The user then writes into the FIFO (see
DATA)” on page
OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXOUTI shall always be cleared before clearing FIFOCON.
The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write fur-
ther data into the FIFO.
Note that if the user decides to switch to the Suspend state (by writing a zero to the
UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and
the bank is sent.
Figure 22-27. Example of an OUT Pipe with one Data Bank
Figure 22-28. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
SW
SW
write data to CPU
write data to CPU
BANK 0
BANK 0
481) and clears the FIFOCON bit to allow the USBB to send the data. If the
SW
OUT
SW
OUT
SW
(bank 0)
DATA
write data to CPU
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
BANK 1
(bank 0)
DATA
ACK
HW
HW
ACK
SW
OUT
SW
SW
write data to CPU
(bank 1)
DATA
write data to CPU
BANK 0
BANK0
AT32UC3B
ACK
SW
OUT
395