ATMEGA644V-10MU Atmel, ATMEGA644V-10MU Datasheet - Page 251

• Manufacturer Part Number: ATMEGA644V-10MU
• Description: IC AVR MCU FLASH 64K 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.9.3
ADLAR = 0
ADLAR = 1
21.9.4
2593N–AVR–07/10
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
• Bit 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use in the ATmega644. For ensuring compability with future
devices, these bits must be written zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x7B)
Read/Write
Initial Value
246.
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
R
7
–
0
ACME
ADC6
ADC8
ADC0
R/W
14
14
R
R
R
R
–
6
0
0
6
0
0
6
0
ADC5
ADC7
13
13
R
R
R
R
R
–
5
0
0
–
5
0
0
5
–
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
R
4
–
0
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
R
3
–
0
ADTS2
ADC2
ADC4
R/W
10
10
R
R
R
R
–
2
0
0
–
2
0
0
2
0
”ADC Conversion Result” on
ADTS1
ADC9
ADC1
ADC3
R/W
R
R
R
R
9
1
0
0
9
–
1
0
0
1
0
ATmega644
ADTS0
ADC8
ADC0
ADC2
R/W
R
R
R
R
8
0
0
0
8
–
0
0
0
0
0
ADCSRB
ADCH
ADCH
ADCL
ADCL
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