ATMEGA644V-10MU Atmel, ATMEGA644V-10MU Datasheet - Page 281

• Manufacturer Part Number: ATMEGA644V-10MU
• Description: IC AVR MCU FLASH 64K 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644V-10MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Package: 44QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: JTAG/SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 24-9.
Note:
See
Programming.
24.9
24.9.1
2593N–AVR–07/10
Variable
PCMSB
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
”Addressing the Flash During Self-Programming” on page 274
1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction.
Register Description
SPMCSR – Store Program Memory Control and Status Register
Explanation of different variables used in
PC[14:7]
PC[6:0]
14
7
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. see
the Signature Row from Software” on page 277
after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use
and should not be used.
Bit
0x37 (0x57)
Read/Write
Initial Value
Correspondig
Z-value
Z15:Z7
Z7:Z1
Z15
Z8
SPMIE
R/W
7
0
RWWSB
Description
Most significant bit in the Program Counter. (The Program Counter is 15 bits
PC[14:0])
Most significant bit which is used to address the words within one page (128
words in a page requires seven bits PC [6:0]).
Bit in Z-pointer that is mapped to PCMSB. Because Z0 is not used, the
ZPCMSB equals PCMSB + 1.
Bit in Z-pointer that is mapped to PCMSB. Because Z0 is not used, the
ZPAGEMSB equals PAGEMSB + 1.
Program Counter page address: Page select, for Page Erase and Page Write
Program Counter word address: Word select, for filling temporary buffer (must
be zero during Page Write operation)
R
6
0
Figure 24-3
SIGRD
R/W
5
0
(1)
RWWSRE
and the mapping to the Z-pointer
R/W
4
0
for details about the use of Z-pointer during Self-
for details. An SPM instruction within four cycles
BLBSET
R/W
3
0
PGWRT
R/W
2
0
PGERS
R/W
1
0
ATmega644
SPMEN
R/W
0
0
”Reading
SPMCSR
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