ATMEGA128A-MU Atmel, ATMEGA128A-MU Datasheet - Page 76
ATMEGA128A-MU
Manufacturer Part Number
ATMEGA128A-MU
Description
MCU 8BIT 128K ISP FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Controller Family/series
AVR MEGA
No. Of I/o's
53
Eeprom Memory Size
4KB
Ram Memory Size
4KB
Cpu Speed
16MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Price
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Part Number:
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12.3.3
8151H–AVR–02/11
Alternate Functions of Port C
Table 12-6.
Note:
Table 12-7.
In ATmega103 compatibility mode, Port C is output only. The ATmega128A is by default
shipped in compatibility mode. Thus, if the parts are not programmed before they are put on the
PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode
is disabled. The Port C has an alternate function as the address high byte for the External Mem-
ory Interface.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. See
ATmega103 compatibility mode.
PB3/MISO
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE OUTPUT
0
0
SPI MSTR INPUT
–
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
“Output Compare Modulator (OCM1C2)” on page 163
PB7/OC2/OC1C
0
0
0
0
OC2/OC1C ENABLE
OC2/OC1C
0
0
–
–
(1)
PB2/MOSI
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
0
0
SPI SLAVE INPUT
–
(1)
PB6/OC1B
0
0
0
OC1B ENABLE
OC1B
0
0
–
–
0
PB1/SCK
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
0
0
SCK INPUT
–
PB5/OC1A
0
0
0
0
OC1A ENABLE
OC1A
0
0
–
–
for details. OC1C does not exist in
ATmega128A
PB0/SS
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
0
0
0
0
SPI SS
–
PB4/OC0
0
0
0
0
OC0 ENABLE
OC0B
0
0
–
–
76
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