LPC3180FEL320,551 NXP Semiconductors, LPC3180FEL320,551 Datasheet - Page 10

• Manufacturer Part Number: LPC3180FEL320,551
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320,551

• Program Memory Type: ROMless
• Package / Case: 320-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C/SPI/UART/USB
• Maximum Clock Frequency: 208 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 2
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, LPC3180-DEV-KIT
• Development Tools By Supplier: OM10096
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 3-ch x 10-bit
• Package: 320LFBGA
• Device Core: ARM926EJ-S
• Family Name: LPC3100
• Maximum Speed: 208 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935281874551; LPC3180FEL320-S; LPC3180FEL320-S

NXP Semiconductors
Table 3.
LPC3180_01_1
Preliminary data sheet
Symbol
RAM_D[16]/
DDR_DQS0
RAM_D[17]/
DDR_DQS1
RAM_D[18]/
DDR_NCLK
RAM_D[31:19]/
PIO_SD[12:00]
RAM_DQM[3:0]
RAM_RAS_N
RAM_WR_N
RESET_N
RESOUT_N
RTCX_IN
RTCX_OUT
SPI1_CLK
SPI1_DATIN
SPI1_DATIO
SPI2_CLK
SPI2_DATIN
SPI2_DATIO
SYSCLKEN
SYSX_IN
SYSX_OUT
TEST (DBGEN)
TST_CLK2
U1_RX/
PIO_INP[15]
U1_TX
U2_HCTS/
PIO_INP[16]
U2_RX/
PIO_INP[17]
U2_TX
U3_RX/
PIO_INP[18]
U3_TX
U5_RX/PIO_INP[20]
LPC 3180/01 Pin description
Pin
L23
L21
K24
E24, E23, F21, F24,
G24, H23, J21, G23,
H22, K23, H24, J24,
H21
W24, V21, W23, Y24 O
U21
V22
D13
AB12
A14
A13
W3
V1
W1
V3
T4
V2
C5
A23
B23
D3
AB3
B9
B10
B8
C7
D9
C6
A7
A2
…continued
Rev. 00.08 — 20 November 2008
I
Type Description
I/O
O
I/O
O
I/O
O
I/O
I/O
O
O
I
O
I
O
O
I/O
O
I
I/O
I/O
I
O
I
O
I
I
O
I
I
I
I
O
I
I
O
I
I
16/32-bit ARM microcontroller with external memory interface
RAM_D[16] — SDRAM data bus, pin 16
DDR_DQS0 — SDRAM data strobe output for lower byte
RAM_D[17] — SDRAM data bus, pin 17
DDR_DQS1 — SDRAM data strobe output for upper byte
RAM_D[18] — SDRAM data bus, pin 18
DDR_NCLK — inverted SDRAM clock output for DDR
RAM_D[31:19] — SDRAM data bus, pins 31 to 19
PIO_SD[12:00] — general purpose input/output, pins 12 to 00;
details may be found in
SDRAM byte write mask outputs
SDRAM row address strobe output
SDRAM write strobe output
system reset input
reset output signal
RTC oscillator input
RTC oscillator output
clock output for SPI1
data input for SPI1
data input/output for SPI1
clock output for SPI2
data input for SPI2
data input/output for SPI2
system clock request
main oscillator input
main oscillator output
test input; internally pulled down, should be left floating in an
application
clock test output 2, controlled by the TEST_CLK
U1_RX — UART 1 receive data input
PIO_INP[15] — general purpose input to PIO_INP_STATE register
UART 1 transmit data output
U2_HCTS — UART 2 hardware flow control (CTS) input
PIO_INP[16] — general purpose input to PIO_INP_STATE register
U2_RX — UART 2 receive data input
PIO_INP[17] — general purpose input to PIO_INP_STATE register
UART 2 transmit data output
U3_RX — UART 3 receive data input
PIO_INP[18] — general purpose input to PIO_INP_STATE register
UART 3 transmit data output
U5_RX — UART 5 receive data input
PIO_INP[20] — general purpose input to PIO_INP_STATE register
Section 6.10
LPC3180/01
© NXP B.V. 2008. All rights reserved.
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