LPC3180FEL320,551 NXP Semiconductors, LPC3180FEL320,551 Datasheet - Page 22

• Manufacturer Part Number: LPC3180FEL320,551
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320,551

• Program Memory Type: ROMless
• Package / Case: 320-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C/SPI/UART/USB
• Maximum Clock Frequency: 208 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 2
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, LPC3180-DEV-KIT
• Development Tools By Supplier: OM10096
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 3-ch x 10-bit
• Package: 320LFBGA
• Device Core: ARM926EJ-S
• Family Name: LPC3100
• Maximum Speed: 208 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935281874551; LPC3180FEL320-S; LPC3180FEL320-S

NXP Semiconductors
LPC3180_01_1
Preliminary data sheet
6.18.1 Features
6.19.1 Features
6.20.1 Features
6.19 Millisecond timer
6.20 Watchdog timer
The high-speed timer includes three match registers that are compared to the
Timer/Counter value. A match can generate an interrupt and cause the Timer/Counter to
either continue to run, stop, or be reset. The high-speed timer also includes two capture
registers that can take a snapshot of the Timer/Counter value when an input signal
transitions. A capture event may also generate an interrupt.
The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to
obtain a lower count rate.
The millisecond timer includes three match registers that are compared to the
Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter
either continue to run, stop, or be reset.
The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit
counter. A match register is compared to the Timer. When configured for watchdog
functionality, a match drives the match output low. The match output is gated with an
enable signal that can generate two different reset signals: one that resets the chip
internally, and another that goes through a programmable pulse generator before it goes
to the external pin RESOUT_N and to the internal chip reset.
•
•
•
•
•
•
•
•
•
•
•
32-bit Timer/Counter with programmable 16-bit prescaler.
Counter or Timer operation.
Two 32-bit capture registers.
Three 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Pause control to stop counting when core is in debug state.
32-bit Timer/Counter, running from the 32 kHz RTC clock.
Counter or Timer operation.
Three 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Pause control to stop counting when core is in debug state.
Programmable 32-bit timer.
Internally resets the device if not periodically reloaded.
Rev. 00.08 — 20 November 2008
16/32-bit ARM microcontroller with external memory interface
LPC3180/01
© NXP B.V. 2008. All rights reserved.
22 of 56