LPC3180FEL320,551 NXP Semiconductors, LPC3180FEL320,551 Datasheet - Page 45

• Manufacturer Part Number: LPC3180FEL320,551
• Description: IC ARM9 MCU 208MHZ 320-LFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3180FEL320,551

• Program Memory Type: ROMless
• Package / Case: 320-LFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 208MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 55
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.3 V
• Data Converters: A/D 3x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 64 KB
• Interface Type: I2C/SPI/UART/USB
• Maximum Clock Frequency: 208 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 2
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, LPC3180-DEV-KIT
• Development Tools By Supplier: OM10096
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 3-ch x 10-bit
• Package: 320LFBGA
• Device Core: ARM926EJ-S
• Family Name: LPC3100
• Maximum Speed: 208 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1018 - EVAL KIT FOR LP3180568-4063 - KIT DEV LPC3180568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935281874551; LPC3180FEL320-S; LPC3180FEL320-S

NXP Semiconductors
Table 14.
LPC3180_01_1
Preliminary data sheet
Fig 17. SPI master timing (CPHA = 0)
Symbol
T
SPI1
t
t
t
t
SPI2
t
t
t
t
SPIDSU
SPIDH
SPIDV
SPIOH
SPIDSU
SPIDH
SPIDV
SPIOH
SPICYC
Dynamic characteristics of SPI pins for LPC3180/01
9.7 SPI controller
Parameter
SPI cycle time
SPI data set-up time
SPI data hold time
SPI enable to output data valid time
SPI output data hold time
SPI data set-up time
SPI data hold time
SPI enable to output data valid time
SPI output data hold time
[1]
SCK (CPOL = 0)
SCK (CPOL = 1)
T
HCLK
SPIn_DATIO
SPIn_DATIN
= period time of SPI IP block input clock (HCLK)
Rev. 00.08 — 20 November 2008
16/32-bit ARM microcontroller with external memory interface
DATA VALID
DATA VALID
t
SPIDV
t
SPICLK
[1]
t
SPIDSU
DATA VALID
DATA VALID
Min
2 T
t
SPICLKH
t
HCLK
SPIDH
002aad326_CPHA0_CW
t
SPICLKL
Typ
6
0
2
0
10
0
2
0
t
SPIOH
LPC3180/01
Max
256 T
© NXP B.V. 2008. All rights reserved.
HCLK
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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