P80C557E4EFB/01,55 NXP Semiconductors, P80C557E4EFB/01,55 Datasheet - Page 14

• Manufacturer Part Number: P80C557E4EFB/01,55
• Description: IC 80C51 MCU 1024 ROMLESS 80QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C557E4EFB/01,55

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 935263156557; P80C557E4FB; P80C557E4FB

Philips Semiconductors
6.4 I/O Facilities
The P8xC557E4 has six 8-bit ports. Ports 0 to 3 are the same as in
the 80C51, with the exception of the additional functions of Port 1.
The parallel I/O function of Port 4 is equal to that of Ports 1, 2 and 3.
Port 5 has a parallel input port function, but has no function as an
output port.
The SDA and SCL lines serve the serial port SIO1 (I
the I
V
Ports 0, 1, 2, 3, 4 and 5 perform the following alternative functions:
1999 Mar 02
Port 0 :
Port 1 :
Port 2 :
Port 3 :
DD,
Single-chip 8-bit microcontroller
2
C-bus may be active while the device is disconnected from
these pins, are provided with open drain drivers.
provides the multiplexed low-order address and data
bus used for expanding the P8xC557E4 with standard
memories and peripherals.
Port 1 is used for a number of special functions:
4 capture inputs (or external interrupt request inputs if
capture information is not utilized)
– external counter input
– external counter reset input
provides the high-order address bus when the
P8xC557E4 is expanded with external Program
Memory and/or external Data Memory.
pins can be configured individually to provide:
– external interrupt request inputs
– counter inputs
– receiver input and transmitter output of seri port
– control signals to read and write external Data
SIO 0 (UART)
Memory
From Port
Latch
QN
During this time, P1 also turns on P3 through the inverter to form an additional pull up.
P1 is turned on for 2 system clock periods after QN makes a 1-to-0 transition.
2 System Clock Periods
Figure 9. I/O buffers in the P8xC557E4 (Ports 1, 2, 3 and 4)
2
C). Because
Read Port Pin
Input Data
14
P83C557E4/P80C557E4/P89C557E4
All ports are bidirectional with the exception of Port 5 which is an
input port.
Pins of which the alternative function is not used may be used as
normal bidirectional I/Os.
The generation or use of a Port 1, Port 3 or Port 4 pin as an
alternative function is carried out automatically by the P8xC557E4
provided the associated Special Function Register bit is set HIGH.
The pull-up arrangements of Ports 1 – 4 are shown in Figure 9.
Port 4 :
Port 5 :
V
DD
P1
n
can be configured to provide signals indicating a match
between timer counter T2 and its compare registers.
may be used in conjunction with the ADC interface.
Unused analog inputs can be used as digital inputs. As
Port 5 lines may be used as inputs to the ADC, these
digital inputs have an inherent hysteresis to prevent the
input logic from drawing too much current from the
power lines when driven by analog signals. Channel to
channel crosstalk should be taken into consideration
when both digital and analog signals are simultaneously
input to Port 5 (see DC characteristics).
V
DD
P2
V
DD
P3
Port
Pin
Product specification