P80C557E4EFB/01,55 NXP Semiconductors, P80C557E4EFB/01,55 Datasheet - Page 62

• Manufacturer Part Number: P80C557E4EFB/01,55
• Description: IC 80C51 MCU 1024 ROMLESS 80QFP
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C557E4EFB/01,55

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 935263156557; P80C557E4FB; P80C557E4FB

Philips Semiconductors
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 55 and 57 through 59 for I
2. The operating supply current is measured with all output pins disconnected;
3. The Idle Mode supply current is measured with all output pins disconnected;
4. The Power-down current is measured with all output pins disconnected;
5. The input threshold voltage of SCL and SDA (SIO1) meets the I
6. Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from HIGH to LOW. The transition current reaches
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
8. Capacitive loading on ports 0 and 2 may cause the V
9. Conditions: AV
10. The differential non-linearity (DL
11. The ADC is monotonic; there are no missing codes.
12. The integral non-linearity (IL
13. The offset error (OS
14. The gain error (G
15. The absolute voltage error (A
16. This should be considered when both analog and digital signals are simultaneously input to port 5.
17. The supply current with 32 kHz oscillator running and PLL operation (SELXTAL1 = 0) is measured with all output pins disconnected;
18. Not 100% tested; sum of A
19. The parameter meets the I
20. Not 100% tested.
1999 Mar 02
Single-chip 8-bit microcontroller
XTAL1 driven with t
EA = RSTIN = Port 0 = EW = SCL = SDA = SELXTAL1 = V
XTAL1 driven with t
Port 0 = EW = SCL = SDA = SELXTAL 1 = V
XTAL2 not connected; Port 0 = EW = SCL = SDA = SELXTAL 1 = V
logic 0 while an input voltage above 0.7 V
its maximum value when V
due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
bits are stabilizing.
by continuous conversion of AV
ADC prescaler programmed according to the actual oscillator frequency, resulting in a conversion time within the specified range for t
(15 s ... 50 s).
appropriate adjustment of gain and offset error.
a straight line which fits the ideal transfer curve. The offset error is constant at every point of the actual transfer curve.
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve.
ADC and the ideal transfer curve.
XTAL4 driven with t
Port 0 = EW = SCL = SDA = V
REF–
e
) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
r
r
r
= 0 V; AV
e
= t
= t
= t
) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
f
f
f
= 5ns; V
= 5ns; V
= 5ns; V
2
IN
IID
C bus specification for standard-mode and fast-mode devices.
e
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
is approximately 2 V.
e
DD
(PLL) and A
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
DD
IN
e
IL
IL
= 5.0 V, AV
IL
) is the difference between the actual step width and the ideal step width.
; EA = RSTIN = ADEXS = SELXTAL 1 = XTAL1 = V
= –20mV to 5.12 V in steps of 0.5mV, derivating parameters from collected conversion results of ADC.
= V
= V
= V
SS
SS
SS
DD
+ 0.5 V; V
+ 0.5 V; V
DD
+ 0.5 V; V
IDD
test conditions.
REF+
DD
will be recognized as a logic 1.
(HF-Oscillator).
; EA = RSTIN = ADEXS = XTAL4 = V
= 5.12 V. V
IH
IH
OH
IH
= V
= V
= V
on ALE and PSEN to momentarily fall below the 0.9V
DD
DD
DD
DD
DD
– 0.5 V; XTAL2, XTAL3 not connected;
– 0.5 V; XTAL2, XTAL3 not connected;
– 0.5 V; XTAL2 not connected;
; ADEXS = XTAL4 = V
2
= 5.0 V, V
C specification, so an input voltage below 0.3 V
62
DD
; EA = RSTIN = ADEXS = XTAL1 = XTAL4 = V
P83C557E4/P80C557E4/P89C557E4
SS
= 0 V, ADC is monotonic with no missing codes. Measurement
SS
SS
SS
.
.
.
OL
of ALE and ports 1, 3 and 4. The noise is
DD
specification when the address
DD
will be recognized as a
SS
Product specification
.
conv